[thirdparty/binutils-gdb.git] / bfd / verilog.c

/* BFD back-end for verilog hex memory dump files.
   Copyright (C) 2009-2024 Free Software Foundation, Inc.
   Written by Anthony Green <green@moxielogic.com>

   This file is part of BFD, the Binary File Descriptor library.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */


/* SUBSECTION
	Verilog hex memory file handling

   DESCRIPTION

	Verilog hex memory files cannot hold anything but addresses
	and data, so that's all that we implement.

	The syntax of the text file is described in the IEEE standard
	for Verilog.  Briefly, the file contains two types of tokens:
	data and optional addresses.  The tokens are separated by
	whitespace and comments.  Comments may be single line or
	multiline, using syntax similar to C++.  Addresses are
	specified by a leading "at" character (@) and are always
	hexadecimal strings.  Data and addresses may contain
	underscore (_) characters.

	If no address is specified, the data is assumed to start at
	address 0.  Similarly, if data exists before the first
	specified address, then that data is assumed to start at
	address 0.


   EXAMPLE
	@1000
	01 ae 3f 45 12

   DESCRIPTION
	@1000 specifies the starting address for the memory data.
	The following characters describe the 5 bytes at 0x1000.  */


#include "sysdep.h"
#include "bfd.h"
#include "libbfd.h"
#include "libiberty.h"
#include "safe-ctype.h"

/* Modified by obcopy.c
   Data width in bytes.  */
unsigned int VerilogDataWidth = 1;

/* Modified by obcopy.c
   Data endianness.  */
enum bfd_endian VerilogDataEndianness = BFD_ENDIAN_UNKNOWN;

/* Macros for converting between hex and binary.  */

static const char digs[] = "0123456789ABCDEF";

#define NIBBLE(x)    hex_value (x)
#define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
#define TOHEX(d, x) \
	d[1] = digs[(x) & 0xf]; \
	d[0] = digs[((x) >> 4) & 0xf];

/* When writing a verilog memory dump file, we write them in the order
   in which they appear in memory. This structure is used to hold them
   in memory.  */

struct verilog_data_list_struct
{
  struct verilog_data_list_struct *next;
  bfd_byte * data;
  bfd_vma where;
  bfd_size_type size;
};

typedef struct verilog_data_list_struct verilog_data_list_type;

/* The verilog tdata information.  */

typedef struct verilog_data_struct
{
  verilog_data_list_type *head;
  verilog_data_list_type *tail;
}
tdata_type;

static bool
verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
{
  if (arch != bfd_arch_unknown)
    return bfd_default_set_arch_mach (abfd, arch, mach);

  abfd->arch_info = & bfd_default_arch_struct;
  return true;
}

/* We have to save up all the output for a splurge before output.  */

static bool
verilog_set_section_contents (bfd *abfd,
			      sec_ptr section,
			      const void * location,
			      file_ptr offset,
			      bfd_size_type bytes_to_do)
{
  tdata_type *tdata = abfd->tdata.verilog_data;
  verilog_data_list_type *entry;

  entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
  if (entry == NULL)
    return false;

  if (bytes_to_do
      && (section->flags & SEC_ALLOC)
      && (section->flags & SEC_LOAD))
    {
      bfd_byte *data;

      data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
      if (data == NULL)
	return false;
      memcpy ((void *) data, location, (size_t) bytes_to_do);

      entry->data = data;
      entry->where = section->lma + offset;
      entry->size = bytes_to_do;

      /* Sort the records by address.  Optimize for the common case of
	 adding a record to the end of the list.  */
      if (tdata->tail != NULL
	  && entry->where >= tdata->tail->where)
	{
	  tdata->tail->next = entry;
	  entry->next = NULL;
	  tdata->tail = entry;
	}
      else
	{
	  verilog_data_list_type **look;

	  for (look = &tdata->head;
	       *look != NULL && (*look)->where < entry->where;
	       look = &(*look)->next)
	    ;
	  entry->next = *look;
	  *look = entry;
	  if (entry->next == NULL)
	    tdata->tail = entry;
	}
    }
  return true;
}

static bool
verilog_write_address (bfd *abfd, bfd_vma address)
{
  char buffer[20];
  char *dst = buffer;
  bfd_size_type wrlen;

  /* Write the address.  */
  *dst++ = '@';
#ifdef BFD64
  if (address >= (bfd_vma)1 << 32)
    {
      TOHEX (dst, (address >> 56));
      dst += 2;
      TOHEX (dst, (address >> 48));
      dst += 2;
      TOHEX (dst, (address >> 40));
      dst += 2;
      TOHEX (dst, (address >> 32));
      dst += 2;
    }
#endif
  TOHEX (dst, (address >> 24));
  dst += 2;
  TOHEX (dst, (address >> 16));
  dst += 2;
  TOHEX (dst, (address >> 8));
  dst += 2;
  TOHEX (dst, (address));
  dst += 2;
  *dst++ = '\r';
  *dst++ = '\n';
  wrlen = dst - buffer;

  return bfd_write (buffer, wrlen, abfd) == wrlen;
}

/* Write a record of type, of the supplied number of bytes. The
   supplied bytes and length don't have a checksum.  That's worked
   out here.  */

static bool
verilog_write_record (bfd *abfd,
		      const bfd_byte *data,
		      const bfd_byte *end)
{
  char buffer[52];
  const bfd_byte *src = data;
  char *dst = buffer;
  bfd_size_type wrlen;

  /* Paranoia - check that we will not overflow "buffer".  */
  if (((end - data) * 2) /* Number of hex characters we want to emit.  */
      + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit.  */
      + 2 /* The carriage return & line feed characters.  */
      > (long) sizeof (buffer))
    {
      /* FIXME: Should we generate an error message ?  */
      return false;
    }

  /* Write the data.
     FIXME: Under some circumstances we can emit a space at the end of
     the line.  This is not really necessary, but catching these cases
     would make the code more complicated.  */
  if (VerilogDataWidth == 1)
    {
      for (src = data; src < end;)
	{
	  TOHEX (dst, *src);
	  dst += 2;
	  src ++;
	  if (src < end)
	    *dst++ = ' ';
	}
    }
  else if ((VerilogDataEndianness == BFD_ENDIAN_UNKNOWN && bfd_little_endian (abfd)) /* FIXME: Can this happen ?  */
	   || (VerilogDataEndianness == BFD_ENDIAN_LITTLE))
    {
      /* If the input byte stream contains:
	   05 04 03 02 01 00
	 and VerilogDataWidth is 4 then we want to emit:
           02030405 0001  */
      int i;

      for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
	{
	  for (i = VerilogDataWidth - 1; i >= 0; i--)
	    {
	      TOHEX (dst, src[i]);
	      dst += 2;
	    }
	  *dst++ = ' ';
	}

      /* Emit any remaining bytes.  Be careful not to read beyond "end".  */
      while (end > src)
	{
	  -- end;
	  TOHEX (dst, *end);
	  dst += 2;
	}

      /* FIXME: Should padding bytes be inserted here ?  */
    }
  else /* Big endian output.  */
    {
      for (src = data; src < end;)
	{
	  TOHEX (dst, *src);
	  dst += 2;
	  ++ src;
	  if ((src - data) % VerilogDataWidth == 0)
	    *dst++ = ' ';
	}
      /* FIXME: Should padding bytes be inserted here ?  */
    }

  *dst++ = '\r';
  *dst++ = '\n';
  wrlen = dst - buffer;

  return bfd_write (buffer, wrlen, abfd) == wrlen;
}

static bool
verilog_write_section (bfd *abfd,
		       tdata_type *tdata ATTRIBUTE_UNUSED,
		       verilog_data_list_type *list)
{
  unsigned int octets_written = 0;
  bfd_byte *location = list->data;

  /* Insist that the starting address is a multiple of the data width.  */
  if (list->where % VerilogDataWidth)
    {
      bfd_set_error (bfd_error_invalid_operation);
      return false;
    }

  verilog_write_address (abfd, list->where / VerilogDataWidth);
  while (octets_written < list->size)
    {
      unsigned int octets_this_chunk = list->size - octets_written;

      if (octets_this_chunk > 16)
	octets_this_chunk = 16;

      if (! verilog_write_record (abfd,
				  location,
				  location + octets_this_chunk))
	return false;

      octets_written += octets_this_chunk;
      location += octets_this_chunk;
    }

  return true;
}

static bool
verilog_write_object_contents (bfd *abfd)
{
  tdata_type *tdata = abfd->tdata.verilog_data;
  verilog_data_list_type *list;

  /* Now wander though all the sections provided and output them.  */
  list = tdata->head;

  while (list != (verilog_data_list_type *) NULL)
    {
      if (! verilog_write_section (abfd, tdata, list))
	return false;
      list = list->next;
    }
  return true;
}

/* Initialize by filling in the hex conversion array.  */

static void
verilog_init (void)
{
  static bool inited = false;

  if (! inited)
    {
      inited = true;
      hex_init ();
    }
}

/* Set up the verilog tdata information.  */

static bool
verilog_mkobject (bfd *abfd)
{
  tdata_type *tdata;

  verilog_init ();

  tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
  if (tdata == NULL)
    return false;

  abfd->tdata.verilog_data = tdata;
  tdata->head = NULL;
  tdata->tail = NULL;

  return true;
}

#define verilog_close_and_cleanup		     _bfd_generic_close_and_cleanup
#define verilog_bfd_free_cached_info		     _bfd_generic_bfd_free_cached_info
#define verilog_new_section_hook		     _bfd_generic_new_section_hook
#define verilog_bfd_is_target_special_symbol	     _bfd_bool_bfd_asymbol_false
#define verilog_bfd_is_local_label_name		     bfd_generic_is_local_label_name
#define verilog_get_lineno			     _bfd_nosymbols_get_lineno
#define verilog_find_nearest_line		     _bfd_nosymbols_find_nearest_line
#define verilog_find_nearest_line_with_alt	     _bfd_nosymbols_find_nearest_line_with_alt
#define verilog_find_inliner_info		     _bfd_nosymbols_find_inliner_info
#define verilog_make_empty_symbol		     _bfd_generic_make_empty_symbol
#define verilog_bfd_make_debug_symbol		     _bfd_nosymbols_bfd_make_debug_symbol
#define verilog_read_minisymbols		     _bfd_generic_read_minisymbols
#define verilog_minisymbol_to_symbol		     _bfd_generic_minisymbol_to_symbol
#define verilog_bfd_get_relocated_section_contents   bfd_generic_get_relocated_section_contents
#define verilog_bfd_relax_section		     bfd_generic_relax_section
#define verilog_bfd_gc_sections			     bfd_generic_gc_sections
#define verilog_bfd_merge_sections		     bfd_generic_merge_sections
#define verilog_bfd_is_group_section		     bfd_generic_is_group_section
#define verilog_bfd_group_name			     bfd_generic_group_name
#define verilog_bfd_discard_group		     bfd_generic_discard_group
#define verilog_section_already_linked		     _bfd_generic_section_already_linked
#define verilog_bfd_link_hash_table_create	     _bfd_generic_link_hash_table_create
#define verilog_bfd_link_add_symbols		     _bfd_generic_link_add_symbols
#define verilog_bfd_link_just_syms		     _bfd_generic_link_just_syms
#define verilog_bfd_final_link			     _bfd_generic_final_link
#define verilog_bfd_link_split_section		     _bfd_generic_link_split_section

const bfd_target verilog_vec =
{
  "verilog",			/* Name.  */
  bfd_target_verilog_flavour,
  BFD_ENDIAN_UNKNOWN,		/* Target byte order.  */
  BFD_ENDIAN_UNKNOWN,		/* Target headers byte order.  */
  (HAS_RELOC | EXEC_P |		/* Object flags.  */
   HAS_LINENO | HAS_DEBUG |
   HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
  (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
   | SEC_ALLOC | SEC_LOAD | SEC_RELOC),	/* Section flags.  */
  0,				/* Leading underscore.  */
  ' ',				/* AR_pad_char.  */
  16,				/* AR_max_namelen.  */
  0,				/* match priority.  */
  TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols.  */
  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
  bfd_getb32, bfd_getb_signed_32, bfd_putb32,
  bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Data.  */
  bfd_getb64, bfd_getb_signed_64, bfd_putb64,
  bfd_getb32, bfd_getb_signed_32, bfd_putb32,
  bfd_getb16, bfd_getb_signed_16, bfd_putb16,	/* Hdrs.  */

  {
    _bfd_dummy_target,
    _bfd_dummy_target,
    _bfd_dummy_target,
    _bfd_dummy_target,
  },
  {
    _bfd_bool_bfd_false_error,
    verilog_mkobject,
    _bfd_bool_bfd_false_error,
    _bfd_bool_bfd_false_error,
  },
  {				/* bfd_write_contents.  */
    _bfd_bool_bfd_false_error,
    verilog_write_object_contents,
    _bfd_bool_bfd_false_error,
    _bfd_bool_bfd_false_error,
  },

  BFD_JUMP_TABLE_GENERIC (_bfd_generic),
  BFD_JUMP_TABLE_COPY (_bfd_generic),
  BFD_JUMP_TABLE_CORE (_bfd_nocore),
  BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
  BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
  BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
  BFD_JUMP_TABLE_WRITE (verilog),
  BFD_JUMP_TABLE_LINK (_bfd_nolink),
  BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),

  NULL,

  NULL
};
Commit	Line	Data
c067354b	1	/* BFD back-end for verilog hex memory dump files.
fd67aa11	2	Copyright (C) 2009-2024 Free Software Foundation, Inc.
c067354b NC	3	Written by Anthony Green <green@moxielogic.com>
	4
	5	This file is part of BFD, the Binary File Descriptor library.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
	9	the Free Software Foundation; either version 3 of the License, or
	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; if not, write to the Free Software
	19	Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
	20	MA 02110-1301, USA. */
	21
	22
	23	/* SUBSECTION
	24	Verilog hex memory file handling
	25
	26	DESCRIPTION
	27
	28	Verilog hex memory files cannot hold anything but addresses
	29	and data, so that's all that we implement.
	30
	31	The syntax of the text file is described in the IEEE standard
	32	for Verilog. Briefly, the file contains two types of tokens:
	33	data and optional addresses. The tokens are separated by
	34	whitespace and comments. Comments may be single line or
	35	multiline, using syntax similar to C++. Addresses are
	36	specified by a leading "at" character (@) and are always
	37	hexadecimal strings. Data and addresses may contain
	38	underscore (_) characters.
	39
	40	If no address is specified, the data is assumed to start at
	41	address 0. Similarly, if data exists before the first
	42	specified address, then that data is assumed to start at
	43	address 0.
	44
	45
	46	EXAMPLE
	47	@1000
07d6d2b8	48	01 ae 3f 45 12
c067354b NC	49
	50	DESCRIPTION
	51	@1000 specifies the starting address for the memory data.
	52	The following characters describe the 5 bytes at 0x1000. */
	53
	54
	55	#include "sysdep.h"
	56	#include "bfd.h"
	57	#include "libbfd.h"
	58	#include "libiberty.h"
	59	#include "safe-ctype.h"
	60
37d0d091 JH	61	/* Modified by obcopy.c
	62	Data width in bytes. */
	63	unsigned int VerilogDataWidth = 1;
	64
6ef35c04 NC	65	/* Modified by obcopy.c
	66	Data endianness. */
	67	enum bfd_endian VerilogDataEndianness = BFD_ENDIAN_UNKNOWN;
	68
c067354b NC	69	/* Macros for converting between hex and binary. */
	70
	71	static const char digs[] = "0123456789ABCDEF";
	72
37d0d091 JH	73	#define NIBBLE(x) hex_value (x)
37d0d091 JH	74	#define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
c067354b NC	75	#define TOHEX(d, x) \
	76	d[1] = digs[(x) & 0xf]; \
	77	d[0] = digs[((x) >> 4) & 0xf];
	78
	79	/* When writing a verilog memory dump file, we write them in the order
	80	in which they appear in memory. This structure is used to hold them
	81	in memory. */
	82
	83	struct verilog_data_list_struct
	84	{
	85	struct verilog_data_list_struct *next;
	86	bfd_byte * data;
	87	bfd_vma where;
	88	bfd_size_type size;
	89	};
	90
	91	typedef struct verilog_data_list_struct verilog_data_list_type;
	92
	93	/* The verilog tdata information. */
	94
	95	typedef struct verilog_data_struct
	96	{
	97	verilog_data_list_type *head;
	98	verilog_data_list_type *tail;
	99	}
	100	tdata_type;
	101
0a1b45a2	102	static bool
c067354b NC	103	verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
	104	{
	105	if (arch != bfd_arch_unknown)
	106	return bfd_default_set_arch_mach (abfd, arch, mach);
	107
	108	abfd->arch_info = & bfd_default_arch_struct;
0a1b45a2	109	return true;
c067354b NC	110	}
c067354b NC	111
6ef35c04	112	/* We have to save up all the output for a splurge before output. */
c067354b	113
0a1b45a2	114	static bool
c067354b NC	115	verilog_set_section_contents (bfd *abfd,
	116	sec_ptr section,
	117	const void * location,
	118	file_ptr offset,
	119	bfd_size_type bytes_to_do)
	120	{
	121	tdata_type *tdata = abfd->tdata.verilog_data;
	122	verilog_data_list_type *entry;
	123
a50b1753	124	entry = (verilog_data_list_type ) bfd_alloc (abfd, sizeof ( entry));
c067354b	125	if (entry == NULL)
0a1b45a2	126	return false;
c067354b NC	127
	128	if (bytes_to_do
	129	&& (section->flags & SEC_ALLOC)
	130	&& (section->flags & SEC_LOAD))
	131	{
	132	bfd_byte *data;
	133
a50b1753	134	data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
c067354b	135	if (data == NULL)
0a1b45a2	136	return false;
c067354b NC	137	memcpy ((void *) data, location, (size_t) bytes_to_do);
	138
	139	entry->data = data;
	140	entry->where = section->lma + offset;
	141	entry->size = bytes_to_do;
	142
	143	/* Sort the records by address. Optimize for the common case of
	144	adding a record to the end of the list. */
	145	if (tdata->tail != NULL
	146	&& entry->where >= tdata->tail->where)
	147	{
	148	tdata->tail->next = entry;
	149	entry->next = NULL;
	150	tdata->tail = entry;
	151	}
	152	else
	153	{
	154	verilog_data_list_type **look;
	155
	156	for (look = &tdata->head;
	157	look != NULL && (look)->where < entry->where;
	158	look = &(*look)->next)
	159	;
	160	entry->next = *look;
	161	*look = entry;
	162	if (entry->next == NULL)
	163	tdata->tail = entry;
	164	}
	165	}
0a1b45a2	166	return true;
c067354b NC	167	}
c067354b NC	168
0a1b45a2	169	static bool
c067354b NC	170	verilog_write_address (bfd *abfd, bfd_vma address)
c067354b NC	171	{
7def0865	172	char buffer[20];
c067354b NC	173	char *dst = buffer;
	174	bfd_size_type wrlen;
	175
	176	/* Write the address. */
	177	*dst++ = '@';
7def0865 NC	178	#ifdef BFD64
	179	if (address >= (bfd_vma)1 << 32)
	180	{
	181	TOHEX (dst, (address >> 56));
	182	dst += 2;
	183	TOHEX (dst, (address >> 48));
	184	dst += 2;
	185	TOHEX (dst, (address >> 40));
	186	dst += 2;
	187	TOHEX (dst, (address >> 32));
	188	dst += 2;
	189	}
	190	#endif
c067354b NC	191	TOHEX (dst, (address >> 24));
	192	dst += 2;
	193	TOHEX (dst, (address >> 16));
	194	dst += 2;
	195	TOHEX (dst, (address >> 8));
	196	dst += 2;
	197	TOHEX (dst, (address));
	198	dst += 2;
	199	*dst++ = '\r';
	200	*dst++ = '\n';
	201	wrlen = dst - buffer;
	202
226f9f4f	203	return bfd_write (buffer, wrlen, abfd) == wrlen;
c067354b NC	204	}
	205
	206	/* Write a record of type, of the supplied number of bytes. The
37d0d091 JH	207	supplied bytes and length don't have a checksum. That's worked
37d0d091 JH	208	out here. */
c067354b	209
0a1b45a2	210	static bool
c067354b NC	211	verilog_write_record (bfd *abfd,
	212	const bfd_byte *data,
	213	const bfd_byte *end)
	214	{
37d0d091	215	char buffer[52];
c067354b NC	216	const bfd_byte *src = data;
	217	char *dst = buffer;
	218	bfd_size_type wrlen;
	219
37d0d091 JH	220	/* Paranoia - check that we will not overflow "buffer". */
	221	if (((end - data) * 2) /* Number of hex characters we want to emit. */
	222	+ ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit. */
	223	+ 2 /* The carriage return & line feed characters. */
	224	> (long) sizeof (buffer))
c067354b	225	{
37d0d091	226	/* FIXME: Should we generate an error message ? */
0a1b45a2	227	return false;
37d0d091 JH	228	}
	229
	230	/* Write the data.
	231	FIXME: Under some circumstances we can emit a space at the end of
	232	the line. This is not really necessary, but catching these cases
	233	would make the code more complicated. */
	234	if (VerilogDataWidth == 1)
	235	{
	236	for (src = data; src < end;)
	237	{
	238	TOHEX (dst, *src);
	239	dst += 2;
	240	src ++;
	241	if (src < end)
	242	*dst++ = ' ';
	243	}
c067354b	244	}
6ef35c04 NC	245	else if ((VerilogDataEndianness == BFD_ENDIAN_UNKNOWN && bfd_little_endian (abfd)) /* FIXME: Can this happen ? */
6ef35c04 NC	246	\|\| (VerilogDataEndianness == BFD_ENDIAN_LITTLE))
37d0d091 JH	247	{
	248	/* If the input byte stream contains:
	249	05 04 03 02 01 00
	250	and VerilogDataWidth is 4 then we want to emit:
	251	02030405 0001 */
	252	int i;
	253
	254	for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
	255	{
	256	for (i = VerilogDataWidth - 1; i >= 0; i--)
	257	{
	258	TOHEX (dst, src[i]);
	259	dst += 2;
	260	}
	261	*dst++ = ' ';
	262	}
	263
	264	/* Emit any remaining bytes. Be careful not to read beyond "end". */
	265	while (end > src)
	266	{
	267	-- end;
	268	TOHEX (dst, *end);
	269	dst += 2;
	270	}
6ef35c04 NC	271
6ef35c04 NC	272	/* FIXME: Should padding bytes be inserted here ? */
37d0d091	273	}
6ef35c04	274	else /* Big endian output. */
37d0d091 JH	275	{
	276	for (src = data; src < end;)
	277	{
	278	TOHEX (dst, *src);
	279	dst += 2;
	280	++ src;
	281	if ((src - data) % VerilogDataWidth == 0)
	282	*dst++ = ' ';
	283	}
6ef35c04	284	/* FIXME: Should padding bytes be inserted here ? */
37d0d091 JH	285	}
37d0d091 JH	286
c067354b NC	287	*dst++ = '\r';
	288	*dst++ = '\n';
	289	wrlen = dst - buffer;
	290
226f9f4f	291	return bfd_write (buffer, wrlen, abfd) == wrlen;
c067354b NC	292	}
c067354b NC	293
0a1b45a2	294	static bool
c067354b NC	295	verilog_write_section (bfd *abfd,
	296	tdata_type *tdata ATTRIBUTE_UNUSED,
	297	verilog_data_list_type *list)
	298	{
	299	unsigned int octets_written = 0;
	300	bfd_byte *location = list->data;
	301
6ef35c04 NC	302	/* Insist that the starting address is a multiple of the data width. */
	303	if (list->where % VerilogDataWidth)
	304	{
	305	bfd_set_error (bfd_error_invalid_operation);
	306	return false;
	307	}
	308
	309	verilog_write_address (abfd, list->where / VerilogDataWidth);
c067354b NC	310	while (octets_written < list->size)
c067354b NC	311	{
c067354b NC	312	unsigned int octets_this_chunk = list->size - octets_written;
	313
	314	if (octets_this_chunk > 16)
	315	octets_this_chunk = 16;
	316
c067354b NC	317	if (! verilog_write_record (abfd,
	318	location,
	319	location + octets_this_chunk))
0a1b45a2	320	return false;
c067354b NC	321
	322	octets_written += octets_this_chunk;
	323	location += octets_this_chunk;
	324	}
	325
0a1b45a2	326	return true;
c067354b NC	327	}
c067354b NC	328
0a1b45a2	329	static bool
c067354b NC	330	verilog_write_object_contents (bfd *abfd)
	331	{
	332	tdata_type *tdata = abfd->tdata.verilog_data;
	333	verilog_data_list_type *list;
	334
	335	/* Now wander though all the sections provided and output them. */
	336	list = tdata->head;
	337
	338	while (list != (verilog_data_list_type *) NULL)
	339	{
	340	if (! verilog_write_section (abfd, tdata, list))
0a1b45a2	341	return false;
c067354b NC	342	list = list->next;
c067354b NC	343	}
0a1b45a2	344	return true;
c067354b NC	345	}
	346
	347	/* Initialize by filling in the hex conversion array. */
	348
	349	static void
	350	verilog_init (void)
	351	{
0a1b45a2	352	static bool inited = false;
c067354b NC	353
	354	if (! inited)
	355	{
0a1b45a2	356	inited = true;
c067354b NC	357	hex_init ();
	358	}
	359	}
	360
	361	/* Set up the verilog tdata information. */
	362
0a1b45a2	363	static bool
c067354b NC	364	verilog_mkobject (bfd *abfd)
	365	{
	366	tdata_type *tdata;
	367
	368	verilog_init ();
	369
a50b1753	370	tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
c067354b	371	if (tdata == NULL)
0a1b45a2	372	return false;
c067354b NC	373
	374	abfd->tdata.verilog_data = tdata;
	375	tdata->head = NULL;
	376	tdata->tail = NULL;
	377
0a1b45a2	378	return true;
c067354b NC	379	}
c067354b NC	380
07d6d2b8 AM	381	#define verilog_close_and_cleanup _bfd_generic_close_and_cleanup
	382	#define verilog_bfd_free_cached_info _bfd_generic_bfd_free_cached_info
	383	#define verilog_new_section_hook _bfd_generic_new_section_hook
d00dd7dc	384	#define verilog_bfd_is_target_special_symbol _bfd_bool_bfd_asymbol_false
07d6d2b8 AM	385	#define verilog_bfd_is_local_label_name bfd_generic_is_local_label_name
	386	#define verilog_get_lineno _bfd_nosymbols_get_lineno
	387	#define verilog_find_nearest_line _bfd_nosymbols_find_nearest_line
6e7a29c7	388	#define verilog_find_nearest_line_with_alt _bfd_nosymbols_find_nearest_line_with_alt
07d6d2b8 AM	389	#define verilog_find_inliner_info _bfd_nosymbols_find_inliner_info
	390	#define verilog_make_empty_symbol _bfd_generic_make_empty_symbol
	391	#define verilog_bfd_make_debug_symbol _bfd_nosymbols_bfd_make_debug_symbol
	392	#define verilog_read_minisymbols _bfd_generic_read_minisymbols
	393	#define verilog_minisymbol_to_symbol _bfd_generic_minisymbol_to_symbol
c067354b	394	#define verilog_bfd_get_relocated_section_contents bfd_generic_get_relocated_section_contents
07d6d2b8 AM	395	#define verilog_bfd_relax_section bfd_generic_relax_section
	396	#define verilog_bfd_gc_sections bfd_generic_gc_sections
	397	#define verilog_bfd_merge_sections bfd_generic_merge_sections
	398	#define verilog_bfd_is_group_section bfd_generic_is_group_section
cb7f4b29	399	#define verilog_bfd_group_name bfd_generic_group_name
07d6d2b8 AM	400	#define verilog_bfd_discard_group bfd_generic_discard_group
	401	#define verilog_section_already_linked _bfd_generic_section_already_linked
	402	#define verilog_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
	403	#define verilog_bfd_link_add_symbols _bfd_generic_link_add_symbols
	404	#define verilog_bfd_link_just_syms _bfd_generic_link_just_syms
	405	#define verilog_bfd_final_link _bfd_generic_final_link
	406	#define verilog_bfd_link_split_section _bfd_generic_link_split_section
c067354b NC	407
	408	const bfd_target verilog_vec =
	409	{
	410	"verilog", /* Name. */
	411	bfd_target_verilog_flavour,
	412	BFD_ENDIAN_UNKNOWN, /* Target byte order. */
	413	BFD_ENDIAN_UNKNOWN, /* Target headers byte order. */
	414	(HAS_RELOC \| EXEC_P \| /* Object flags. */
	415	HAS_LINENO \| HAS_DEBUG \|
	416	HAS_SYMS \| HAS_LOCALS \| WP_TEXT \| D_PAGED),
	417	(SEC_CODE \| SEC_DATA \| SEC_ROM \| SEC_HAS_CONTENTS
	418	\| SEC_ALLOC \| SEC_LOAD \| SEC_RELOC), /* Section flags. */
	419	0, /* Leading underscore. */
	420	' ', /* AR_pad_char. */
	421	16, /* AR_max_namelen. */
0aabe54e	422	0, /* match priority. */
d1bcae83	423	TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */
c067354b NC	424	bfd_getb64, bfd_getb_signed_64, bfd_putb64,
	425	bfd_getb32, bfd_getb_signed_32, bfd_putb32,
	426	bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Data. */
	427	bfd_getb64, bfd_getb_signed_64, bfd_putb64,
	428	bfd_getb32, bfd_getb_signed_32, bfd_putb32,
	429	bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* Hdrs. */
	430
	431	{
	432	_bfd_dummy_target,
	433	_bfd_dummy_target,
	434	_bfd_dummy_target,
	435	_bfd_dummy_target,
	436	},
	437	{
d00dd7dc	438	_bfd_bool_bfd_false_error,
c067354b	439	verilog_mkobject,
d00dd7dc AM	440	_bfd_bool_bfd_false_error,
d00dd7dc AM	441	_bfd_bool_bfd_false_error,
c067354b NC	442	},
c067354b NC	443	{ /* bfd_write_contents. */
d00dd7dc	444	_bfd_bool_bfd_false_error,
c067354b	445	verilog_write_object_contents,
d00dd7dc AM	446	_bfd_bool_bfd_false_error,
d00dd7dc AM	447	_bfd_bool_bfd_false_error,
c067354b NC	448	},
	449
	450	BFD_JUMP_TABLE_GENERIC (_bfd_generic),
	451	BFD_JUMP_TABLE_COPY (_bfd_generic),
	452	BFD_JUMP_TABLE_CORE (_bfd_nocore),
	453	BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
	454	BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
	455	BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
	456	BFD_JUMP_TABLE_WRITE (verilog),
	457	BFD_JUMP_TABLE_LINK (_bfd_nolink),
	458	BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
	459
	460	NULL,
	461
	462	NULL
	463	};