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common: Drop init.h from common header
[thirdparty/u-boot.git] / board / BuR / brppt2 / board.c
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c04ac5bd
HS		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board functions for BuR BRPPT2 board
4 *
5 * Copyright (C) 2019
6 * B&R Industrial Automation GmbH - http://www.br-automation.com/
7 *
8 */
9#include <common.h>
9a3b4ceb 10#include <cpu_func.h>
db41d65a 11#include <hang.h>
691d719d 12#include <init.h>
c04ac5bd
HS		 13#include <spl.h>
14#include <dm.h>
15#include <miiphy.h>
16#include <asm/arch/crm_regs.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/iomux.h>
19#include <asm/arch/mx6-pins.h>
20#ifdef CONFIG_SPL_BUILD
21# include <asm/arch/mx6-ddr.h>
22#endif
23#include <asm/arch/clock.h>
24#include <asm/io.h>
25#include <asm/gpio.h>
26
27#define USBHUB_RSTN IMX_GPIO_NR(1, 16)
28#define BKLT_EN IMX_GPIO_NR(1, 15)
29#define CAPT_INT IMX_GPIO_NR(4, 9)
30#define CAPT_RESETN IMX_GPIO_NR(4, 11)
31#define SW_INTN IMX_GPIO_NR(3, 26)
32#define VCCDISP_EN IMX_GPIO_NR(5, 18)
33#define EMMC_RSTN IMX_GPIO_NR(6, 8)
34#define PMIC_IRQN IMX_GPIO_NR(5, 22)
35#define TASTER IMX_GPIO_NR(5, 23)
36
37#define ETH0_LINK IMX_GPIO_NR(1, 27)
38#define ETH1_LINK IMX_GPIO_NR(1, 28)
39
40#define UART_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
42 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
43
44#define I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
45 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
46 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
47
48#define ECSPI_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_48ohm | \
50 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
51#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
52 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
53 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
54
55#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
56 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
57 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
58
59#define ENET_PAD_CTRL1 (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
61 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
62
63#define ENET_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
64 PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
65 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
66
67#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
68 PAD_CTL_SPEED_MED | PAD_CTL_DSE_60ohm | \
69 PAD_CTL_SRE_FAST)
70
71#define GPIO_PAD_CTRL_PU (PAD_CTL_PUS_100K_UP | \
72 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
73 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
74
75#define GPIO_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
76 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_48ohm | \
77 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
78
79#define LCDCMOS_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | \
80 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm |\
81 PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
82
83#define MUXDESC(pad, ctrl) IOMUX_PADS(pad | MUX_PAD_CTRL(ctrl))
84
85#if !defined(CONFIG_SPL_BUILD)
86static iomux_v3_cfg_t const eth_pads[] = {
87 /*
88 * Gigabit Ethernet
89 */
90 /* CLKs */
91 MUXDESC(PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL_CLK),
92 MUXDESC(PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL_CLK),
93 /* MDIO */
94 MUXDESC(PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL_PU),
95 MUXDESC(PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL_PU),
96 /* RGMII */
97 MUXDESC(PAD_RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL1),
98 MUXDESC(PAD_RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
99 MUXDESC(PAD_RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
100 MUXDESC(PAD_RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
101 MUXDESC(PAD_RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
102 MUXDESC(PAD_RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
103 MUXDESC(PAD_RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL_PU),
104 MUXDESC(PAD_RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL_PU),
105 MUXDESC(PAD_RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL_PU),
106 MUXDESC(PAD_RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL_PU),
107 MUXDESC(PAD_RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL_PU),
108 MUXDESC(PAD_RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL_PU),
109 /* ETH0_LINK */
110 MUXDESC(PAD_ENET_RXD0__GPIO1_IO27, GPIO_PAD_CTRL_PD),
111 /* ETH1_LINK */
112 MUXDESC(PAD_ENET_TX_EN__GPIO1_IO28, GPIO_PAD_CTRL_PD),
113};
114
115static iomux_v3_cfg_t const board_pads[] = {
116 /*
117 * I2C #3, #4
118 */
119 MUXDESC(PAD_GPIO_3__I2C3_SCL, I2C_PAD_CTRL),
120 MUXDESC(PAD_GPIO_6__I2C3_SDA, I2C_PAD_CTRL),
121
122 /*
123 * UART#4 PADS
124 * UART_Tasten
125 */
126 MUXDESC(PAD_CSI0_DAT12__UART4_TX_DATA, UART_PAD_CTRL),
127 MUXDESC(PAD_CSI0_DAT13__UART4_RX_DATA, UART_PAD_CTRL),
128 MUXDESC(PAD_CSI0_DAT17__UART4_CTS_B, UART_PAD_CTRL),
129 MUXDESC(PAD_CSI0_DAT16__UART4_RTS_B, UART_PAD_CTRL),
130 /*
131 * ESCPI#1
132 * M25P32 NOR-Flash
133 */
134 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
135 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
136 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
137 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
138 /*
139 * ESCPI#2
140 * resTouch SPI ADC
141 */
142 MUXDESC(PAD_CSI0_DAT8__ECSPI2_SCLK, ECSPI_PAD_CTRL),
143 MUXDESC(PAD_EIM_OE__ECSPI2_MISO, ECSPI_PAD_CTRL),
144 MUXDESC(PAD_CSI0_DAT9__ECSPI2_MOSI, ECSPI_PAD_CTRL),
145 MUXDESC(PAD_EIM_D24__GPIO3_IO24, ECSPI_PAD_CTRL),
146 /*
147 * USDHC#4
148 */
149 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
150 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
151 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
152 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
153 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
154 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
155 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
156 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
157 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
158 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
159 /*
160 * USB OTG power & ID
161 */
162 /* USB_OTG_5V_EN */
163 MUXDESC(PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL_PD),
164 MUXDESC(PAD_EIM_D31__GPIO3_IO31, GPIO_PAD_CTRL_PD),
165 /* USB_OTG_JUMPER */
166 MUXDESC(PAD_ENET_RX_ER__USB_OTG_ID, GPIO_PAD_CTRL_PD),
167 /*
168 * PWM-Pins
169 */
170 /* BKLT_CTL */
171 MUXDESC(PAD_SD1_CMD__PWM4_OUT, GPIO_PAD_CTRL_PD),
172 /* SPEAKER */
173 MUXDESC(PAD_SD1_DAT1__PWM3_OUT, GPIO_PAD_CTRL_PD),
174 /*
175 * GPIOs
176 */
177 /* USB_HUB_nRESET */
178 MUXDESC(PAD_SD1_DAT0__GPIO1_IO16, GPIO_PAD_CTRL_PD),
179 /* BKLT_EN */
180 MUXDESC(PAD_SD2_DAT0__GPIO1_IO15, GPIO_PAD_CTRL_PD),
181 /* capTouch_INT */
182 MUXDESC(PAD_KEY_ROW1__GPIO4_IO09, GPIO_PAD_CTRL_PD),
183 /* capTouch_nRESET */
184 MUXDESC(PAD_KEY_ROW2__GPIO4_IO11, GPIO_PAD_CTRL_PD),
185 /* SW_nINT */
186 MUXDESC(PAD_EIM_D26__GPIO3_IO26, GPIO_PAD_CTRL_PU),
187 /* VCC_DISP_EN */
188 MUXDESC(PAD_CSI0_PIXCLK__GPIO5_IO18, GPIO_PAD_CTRL_PD),
189 /* eMMC_nRESET */
190 MUXDESC(PAD_NANDF_ALE__GPIO6_IO08, GPIO_PAD_CTRL_PD),
191 /* HWID*/
192 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
193 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
194 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
195 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
196 /* PMIC_nIRQ */
197 MUXDESC(PAD_CSI0_DAT4__GPIO5_IO22, GPIO_PAD_CTRL_PU),
198 /* nTASTER */
199 MUXDESC(PAD_CSI0_DAT5__GPIO5_IO23, GPIO_PAD_CTRL_PU),
200 /* RGB LCD Display */
201 MUXDESC(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, LCDCMOS_PAD_CTRL),
202 MUXDESC(PAD_DI0_PIN2__IPU1_DI0_PIN02, LCDCMOS_PAD_CTRL),
203 MUXDESC(PAD_DI0_PIN3__IPU1_DI0_PIN03, LCDCMOS_PAD_CTRL),
204 MUXDESC(PAD_DI0_PIN4__IPU1_DI0_PIN04, LCDCMOS_PAD_CTRL),
205 MUXDESC(PAD_DI0_PIN15__IPU1_DI0_PIN15, LCDCMOS_PAD_CTRL),
206 MUXDESC(PAD_DISP0_DAT0__IPU1_DISP0_DATA00, LCDCMOS_PAD_CTRL),
207 MUXDESC(PAD_DISP0_DAT1__IPU1_DISP0_DATA01, LCDCMOS_PAD_CTRL),
208 MUXDESC(PAD_DISP0_DAT2__IPU1_DISP0_DATA02, LCDCMOS_PAD_CTRL),
209 MUXDESC(PAD_DISP0_DAT3__IPU1_DISP0_DATA03, LCDCMOS_PAD_CTRL),
210 MUXDESC(PAD_DISP0_DAT4__IPU1_DISP0_DATA04, LCDCMOS_PAD_CTRL),
211 MUXDESC(PAD_DISP0_DAT5__IPU1_DISP0_DATA05, LCDCMOS_PAD_CTRL),
212 MUXDESC(PAD_DISP0_DAT6__IPU1_DISP0_DATA06, LCDCMOS_PAD_CTRL),
213 MUXDESC(PAD_DISP0_DAT7__IPU1_DISP0_DATA07, LCDCMOS_PAD_CTRL),
214 MUXDESC(PAD_DISP0_DAT8__IPU1_DISP0_DATA08, LCDCMOS_PAD_CTRL),
215 MUXDESC(PAD_DISP0_DAT9__IPU1_DISP0_DATA09, LCDCMOS_PAD_CTRL),
216 MUXDESC(PAD_DISP0_DAT10__IPU1_DISP0_DATA10, LCDCMOS_PAD_CTRL),
217 MUXDESC(PAD_DISP0_DAT11__IPU1_DISP0_DATA11, LCDCMOS_PAD_CTRL),
218 MUXDESC(PAD_DISP0_DAT12__IPU1_DISP0_DATA12, LCDCMOS_PAD_CTRL),
219 MUXDESC(PAD_DISP0_DAT13__IPU1_DISP0_DATA13, LCDCMOS_PAD_CTRL),
220 MUXDESC(PAD_DISP0_DAT14__IPU1_DISP0_DATA14, LCDCMOS_PAD_CTRL),
221 MUXDESC(PAD_DISP0_DAT15__IPU1_DISP0_DATA15, LCDCMOS_PAD_CTRL),
222 MUXDESC(PAD_DISP0_DAT16__IPU1_DISP0_DATA16, LCDCMOS_PAD_CTRL),
223 MUXDESC(PAD_DISP0_DAT17__IPU1_DISP0_DATA17, LCDCMOS_PAD_CTRL),
224 MUXDESC(PAD_DISP0_DAT18__IPU1_DISP0_DATA18, LCDCMOS_PAD_CTRL),
225 MUXDESC(PAD_DISP0_DAT19__IPU1_DISP0_DATA19, LCDCMOS_PAD_CTRL),
226 MUXDESC(PAD_DISP0_DAT20__IPU1_DISP0_DATA20, LCDCMOS_PAD_CTRL),
227 MUXDESC(PAD_DISP0_DAT21__IPU1_DISP0_DATA21, LCDCMOS_PAD_CTRL),
228 MUXDESC(PAD_DISP0_DAT22__IPU1_DISP0_DATA22, LCDCMOS_PAD_CTRL),
229 MUXDESC(PAD_DISP0_DAT23__IPU1_DISP0_DATA23, LCDCMOS_PAD_CTRL),
230};
231
232int board_ehci_hcd_init(int port)
233{
234 gpio_direction_output(USBHUB_RSTN, 1);
235
236 return 0;
237}
238
239int board_late_init(void)
240{
241 ulong b_mode = 4;
242
243 if (gpio_get_value(TASTER) == 0)
244 b_mode = 12;
245
246 env_set_ulong("b_mode", b_mode);
247
248 return 0;
249}
250
251int board_init(void)
252{
253 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
254
255 if (gpio_request(BKLT_EN, "BKLT_EN"))
256 printf("Warning: BKLT_EN setup failed\n");
257 gpio_direction_output(BKLT_EN, 0);
258
259 if (gpio_request(USBHUB_RSTN, "USBHUB_nRST"))
260 printf("Warning: USBHUB_nRST setup failed\n");
261 gpio_direction_output(USBHUB_RSTN, 0);
262
263 if (gpio_request(TASTER, "TASTER"))
264 printf("Warning: TASTER setup failed\n");
265 gpio_direction_input(TASTER);
266
267 return 0;
268}
269
270int board_early_init_f(void)
271{
272 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
273
274 SETUP_IOMUX_PADS(board_pads);
275 SETUP_IOMUX_PADS(eth_pads);
276
277 /* set GPIO_16 as ENET_REF_CLK_OUT running at 25 MHz */
278 setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
279 enable_fec_anatop_clock(0, ENET_25MHZ);
280 enable_enet_clk(1);
281
282 return 0;
283}
284
285int dram_init(void)
286{
287 gd->ram_size = imx_ddr_size();
288
289 return 0;
290}
291#else
292/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
293static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = {
294 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
295 .dram_sdclk_0 = 0x00020030,
296 .dram_sdclk_1 = 0x00020030,
297 .dram_cas = 0x00020030,
298 .dram_ras = 0x00020030,
299 .dram_reset = 0x00020030,
300 /* SDCKE[0:1]: 100k pull-up */
301 .dram_sdcke0 = 0x00003000,
302 .dram_sdcke1 = 0x00003000,
303 /* SDBA2: pull-up disabled */
304 .dram_sdba2 = 0x00000000,
305 /* SDODT[0:1]: 100k pull-up, 40 ohm */
306 .dram_sdodt0 = 0x00003030,
307 .dram_sdodt1 = 0x00003030,
308 /* SDQS[0:7]: Differential input, 40 ohm */
309 .dram_sdqs0 = 0x00000030,
310 .dram_sdqs1 = 0x00000030,
311 .dram_sdqs2 = 0x00000030,
312 .dram_sdqs3 = 0x00000030,
313 .dram_sdqs4 = 0x00000030,
314 .dram_sdqs5 = 0x00000030,
315 .dram_sdqs6 = 0x00000030,
316 .dram_sdqs7 = 0x00000030,
317 /* DQM[0:7]: Differential input, 40 ohm */
318 .dram_dqm0 = 0x00020030,
319 .dram_dqm1 = 0x00020030,
320 .dram_dqm2 = 0x00020030,
321 .dram_dqm3 = 0x00020030,
322 .dram_dqm4 = 0x00020030,
323 .dram_dqm5 = 0x00020030,
324 .dram_dqm6 = 0x00020030,
325 .dram_dqm7 = 0x00020030,
326};
327
328/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
329static struct mx6sdl_iomux_grp_regs grp_iomux_s = {
330 /* DDR3 */
331 .grp_ddr_type = 0x000c0000,
332 .grp_ddrmode_ctl = 0x00020000,
333 /* disable DDR pullups */
334 .grp_ddrpke = 0x00000000,
335 /* ADDR[00:16], SDBA[0:1]: 40 ohm */
336 .grp_addds = 0x00000030,
337 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
338 .grp_ctlds = 0x00000030,
339 /* DATA[00:63]: Differential input, 40 ohm */
340 .grp_ddrmode = 0x00020000,
341 .grp_b0ds = 0x00000030,
342 .grp_b1ds = 0x00000030,
343 .grp_b2ds = 0x00000030,
344 .grp_b3ds = 0x00000030,
345 .grp_b4ds = 0x00000030,
346 .grp_b5ds = 0x00000030,
347 .grp_b6ds = 0x00000030,
348 .grp_b7ds = 0x00000030,
349};
350
351/*
352 * DDR3 desriptions - these are the memory chips we support
353 */
354
355/* NT5CC128M16FP-DII */
356static struct mx6_ddr3_cfg cfg_nt5cc128m16fp_dii = {
357 .mem_speed = 1600,
358 .density = 2,
359 .width = 16,
360 .banks = 8,
361 .rowaddr = 14,
362 .coladdr = 10,
363 .pagesz = 2,
364 .trcd = 1375,
365 .trcmin = 4875,
366 .trasmin = 3500,
367};
368
369/* measured on board TSERIES_ARM/1 V_LVDS_DL64 */
370static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x64_s = {
371 /* write leveling calibration determine, MR1-value = 0x0002 */
372 .p0_mpwldectrl0 = 0x003F003E,
373 .p0_mpwldectrl1 = 0x003A003A,
374 .p1_mpwldectrl0 = 0x001B001C,
375 .p1_mpwldectrl1 = 0x00190031,
376 /* Read DQS Gating calibration */
377 .p0_mpdgctrl0 = 0x02640264,
378 .p0_mpdgctrl1 = 0x02440250,
379 .p1_mpdgctrl0 = 0x02400250,
380 .p1_mpdgctrl1 = 0x0238023C,
381 /* Read Calibration: DQS delay relative to DQ read access */
382 .p0_mprddlctl = 0x40464644,
383 .p1_mprddlctl = 0x464A4842,
384 /* Write Calibration: DQ/DM delay relative to DQS write access */
385 .p0_mpwrdlctl = 0x38343034,
386 .p1_mpwrdlctl = 0x36323830,
387};
388
389/* measured on board TSERIES_ARM/1 V_LVDS_S32 */
390static struct mx6_mmdc_calibration cal_nt5cc128m16fp_dii_128x32_s = {
391 /* write leveling calibration determine, MR1-value = 0x0002 */
392 .p0_mpwldectrl0 = 0x00410043,
393 .p0_mpwldectrl1 = 0x003A003C,
394 /* Read DQS Gating calibration */
395 .p0_mpdgctrl0 = 0x023C0244,
396 .p0_mpdgctrl1 = 0x02240230,
397 /* Read Calibration: DQS delay relative to DQ read access */
398 .p0_mprddlctl = 0x484C4A48,
399 /* Write Calibration: DQ/DM delay relative to DQS write access */
400 .p0_mpwrdlctl = 0x3C363434,
401};
402
403static void spl_dram_init(void)
404{
405 struct gpio_regs *gpio = (struct gpio_regs *)GPIO2_BASE_ADDR;
406 u32 val, dram_strap = 0;
407 struct mx6_ddr3_cfg *mem = NULL;
408 struct mx6_mmdc_calibration *calib = NULL;
409 struct mx6_ddr_sysinfo sysinfo = {
410 /* width of data bus:0=16,1=32,2=64 */
411 .dsize = -1, /* CPU type specific (overwritten) */
412 /* config for full 4GB range so that get_mem_size() works */
413 .cs_density = 32, /* 32Gb per CS */
414 .ncs = 1, /* single chip select */
415 .cs1_mirror = 0,
416 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
417 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
418 .walat = 1, /* Write additional latency */
419 .ralat = 5, /* Read additional latency */
420 .mif3_mode = 3, /* Command prediction working mode */
421 .bi_on = 1, /* Bank interleaving enabled */
422 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
423 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
424 .ddr_type = 0, /* DDR3 */
425 };
426
427 /*
428 * MMDC Calibration requires the following data:
429 * mx6_mmdc_calibration - board-specific calibration (routing delays)
430 * these calibration values depend on board routing, SoC, and DDR
431 * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
432 * mx6_ddr_cfg - chip specific timing/layout details
433 */
434
435 /* setup HWID3-2 to input */
436 val = readl(&gpio->gpio_dir);
437 val &= ~(0x1 << 0 | 0x1 << 1);
438 writel(val, &gpio->gpio_dir);
439
440 /* read DRAM strapping from HWID3/2 (bit 1 and bit 0) */
441 dram_strap = readl(&gpio->gpio_psr) & 0x3;
442
443 switch (dram_strap) {
444 /* 1 GiB, 64 bit, 4 NT5CC128M16FP chips */
445 case 0:
446 puts("DRAM strap 00\n");
447 mem = &cfg_nt5cc128m16fp_dii;
448 sysinfo.dsize = 2;
449 calib = &cal_nt5cc128m16fp_dii_128x64_s;
450 break;
451 /* 512 MiB, 32 bit, 2 NT5CC128M16FP chips */
452 case 1:
453 puts("DRAM strap 01\n");
454 mem = &cfg_nt5cc128m16fp_dii;
455 sysinfo.dsize = 1;
456 calib = &cal_nt5cc128m16fp_dii_128x32_s;
457 break;
458 default:
459 printf("DRAM strap 0x%x (invalid)\n", dram_strap);
460 break;
461 }
462
463 if (!mem) {
464 puts("Error: Invalid Memory Configuration\n");
465 hang();
466 }
467 if (!calib) {
468 puts("Error: Invalid Board Calibration Configuration\n");
469 hang();
470 }
471
472 mx6sdl_dram_iocfg(16 << sysinfo.dsize,
473 &ddr_iomux_s,
474 &grp_iomux_s);
475
476 mx6_dram_cfg(&sysinfo, calib, mem);
477}
478
479static iomux_v3_cfg_t const board_pads_spl[] = {
480 /* UART#1 PADS */
481 MUXDESC(PAD_CSI0_DAT10__UART1_TX_DATA, UART_PAD_CTRL),
482 MUXDESC(PAD_CSI0_DAT11__UART1_RX_DATA, UART_PAD_CTRL),
483 /* ESCPI#1 PADS */
484 MUXDESC(PAD_EIM_D16__ECSPI1_SCLK, ECSPI_PAD_CTRL),
485 MUXDESC(PAD_EIM_D17__ECSPI1_MISO, ECSPI_PAD_CTRL),
486 MUXDESC(PAD_EIM_D18__ECSPI1_MOSI, ECSPI_PAD_CTRL),
487 MUXDESC(PAD_EIM_D19__GPIO3_IO19, ECSPI_PAD_CTRL),
488 /* USDHC#4 PADS */
489 MUXDESC(PAD_SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
490 MUXDESC(PAD_SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
491 MUXDESC(PAD_SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
492 MUXDESC(PAD_SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
493 MUXDESC(PAD_SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
494 MUXDESC(PAD_SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
495 MUXDESC(PAD_SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
496 MUXDESC(PAD_SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
497 MUXDESC(PAD_SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
498 MUXDESC(PAD_SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
499 /* HWID*/
500 MUXDESC(PAD_NANDF_D0__GPIO2_IO00, GPIO_PAD_CTRL_PU),
501 MUXDESC(PAD_NANDF_D1__GPIO2_IO01, GPIO_PAD_CTRL_PU),
502 MUXDESC(PAD_NANDF_D2__GPIO2_IO02, GPIO_PAD_CTRL_PU),
503 MUXDESC(PAD_NANDF_D3__GPIO2_IO03, GPIO_PAD_CTRL_PU),
504};
505
506void spl_board_init(void)
507{
508 preloader_console_init();
509}
510
511static void ccgr_init(void)
512{
513 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
514
515 /*
516 * We don't use DMA in SPL, but we do need it in U-Boot. U-Boot
517 * initializes DMA very early (before all board code), so the only
518 * opportunity we have to initialize APBHDMA clocks is in SPL.
519 * setbits_le32(&ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
520 */
521
522 writel(0x00C03F3F, &ccm->CCGR0);
523 writel(0x00F0FC03, &ccm->CCGR1);
524 writel(0x0FFFF000, &ccm->CCGR2);
525 writel(0x3FF00000, &ccm->CCGR3);
526 writel(0x00FFF300, &ccm->CCGR4);
527 writel(0x0F0030C3, &ccm->CCGR5);
528 writel(0x000003F0, &ccm->CCGR6);
529}
530
531void board_init_f(ulong dummy)
532{
533 ccgr_init();
534 arch_cpu_init();
535 timer_init();
536 gpr_init();
537
538 SETUP_IOMUX_PADS(board_pads_spl);
539 spl_dram_init();
540}
541
542void reset_cpu(ulong addr)
543{
544}
545#endif /* CONFIG_SPL_BUILD */
"Das U-Boot" Source Tree