[thirdparty/u-boot.git] / board / BuR / brxre1 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * board.c
 *
 * Board functions for B&R BRXRE1 Board
 *
 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
 *
 */
#include <env.h>
#include <errno.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <dm.h>
#include <power/tps65217.h>
#include "../common/bur_common.h"
#include "../common/br_resetc.h"

/* -------------------------------------------------------------------------*/
/* -- defines for used GPIO Hardware -- */
#define ESC_KEY					(0 + 19)
#define LCD_PWR					(0 + 5)

#define	RSTCTRL_FORCE_PWR_NEN			0x04
#define	RSTCTRL_CAN_STB				0x40

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_SPL_BUILD)
static const struct ddr_data ddr3_data = {
	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = MT41K256M16HA125E_RATIO,
	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd1csratio = MT41K256M16HA125E_RATIO,
	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,

	.cmd2csratio = MT41K256M16HA125E_RATIO,
	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};

static struct emif_regs ddr3_emif_reg_data = {
	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};

static const struct ctrl_ioregs ddr3_ioregs = {
	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};

#define OSC	(V_OSCK / 1000000)
const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};

void am33xx_spl_board_init(void)
{
	int rc;

	struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
	struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
	/*
	 * enable additional clocks of modules which are accessed later from
	 * VxWorks OS
	 */
	u32 *const clk_domains[] = { 0 };

	u32 *const clk_modules_xre1specific[] = {
		&cmwkup->wkup_adctscctrl,
		&cmper->spi1clkctrl,
		&cmper->dcan0clkctrl,
		&cmper->dcan1clkctrl,
		&cmper->epwmss0clkctrl,
		&cmper->epwmss1clkctrl,
		&cmper->epwmss2clkctrl,
		&cmper->lcdclkctrl,
		&cmper->lcdcclkstctrl,
		0
	};
	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
	/* power-OFF LCD-Display */
	if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
		printf("cannot request gpio for LCD_PWR!\n");
	else if (gpio_direction_output(LCD_PWR, 0) != 0)
		printf("cannot set direction output on LCD_PWR!\n");

	/* setup I2C */
	enable_i2c_pin_mux();

	/* power-ON 3V3 via Resetcontroller */
	rc = br_resetc_regset(RSTCTRL_CTRLREG,
			      RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB);
	if (rc != 0)
		printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");

	pmicsetup(0, 0);
}

const struct dpll_params *get_dpll_ddr_params(void)
{
	return &dpll_ddr3;
}

void sdram_init(void)
{
	config_ddr(400, &ddr3_ioregs,
		   &ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SPL_BUILD */
/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	/* request common used gpios */
	gpio_request(ESC_KEY, "boot-key");

	if (power_tps65217_init(0))
		printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");

	return 0;
}

#ifdef CONFIG_BOARD_LATE_INIT

int board_boot_key(void)
{
	return gpio_get_value(ESC_KEY);
}

int board_late_init(void)
{
	char othbootargs[128];

	br_resetc_bmode();

	/* setup othbootargs for bootvx-command (vxWorks bootline) */
	snprintf(othbootargs, sizeof(othbootargs),
		 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
		 (u32)gd->relocaddr,
		 (u32)env_get_ulong("vx_memtop", 16, gd->relocaddr),
		 (u32)env_get_ulong("vx_romfsbase", 16, 0),
		 (u32)env_get_ulong("vx_romfssize", 16, 0));
	env_set("othbootargs", othbootargs);
	/*
	 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
	 * expect that vectors are there, original u-boot moves them to _start
	 */
	__asm__("ldr r0,=0x20000");
	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */

	return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
072cefe0 HP	2	/*
	3	* board.c
	4	*
a4d79993	5	* Board functions for B&R BRXRE1 Board
072cefe0	6	*
4c302b9a	7	* Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
072cefe0 HP	8	* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
072cefe0 HP	9	*
072cefe0	10	*/
9eef56db	11	#include <env.h>
072cefe0	12	#include <errno.h>
5255932f	13	#include <init.h>
072cefe0 HP	14	#include <spl.h>
	15	#include <asm/arch/cpu.h>
	16	#include <asm/arch/hardware.h>
	17	#include <asm/arch/omap.h>
	18	#include <asm/arch/ddr_defs.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/gpio.h>
	21	#include <asm/arch/sys_proto.h>
	22	#include <asm/arch/mem.h>
401d1c4f	23	#include <asm/global_data.h>
072cefe0 HP	24	#include <asm/io.h>
	25	#include <asm/emif.h>
	26	#include <asm/gpio.h>
eaba7df7	27	#include <dm.h>
072cefe0 HP	28	#include <power/tps65217.h>
072cefe0 HP	29	#include "../common/bur_common.h"
1d260739	30	#include "../common/br_resetc.h"
072cefe0 HP	31
	32	/* -------------------------------------------------------------------------*/
	33	/* -- defines for used GPIO Hardware -- */
2b1e2424 HS	34	#define ESC_KEY (0 + 19)
2b1e2424 HS	35	#define LCD_PWR (0 + 5)
072cefe0	36
1d260739 HS	37	#define RSTCTRL_FORCE_PWR_NEN 0x04
1d260739 HS	38	#define RSTCTRL_CAN_STB 0x40
072cefe0	39
a9642925 HP	40	DECLARE_GLOBAL_DATA_PTR;
a9642925 HP	41
072cefe0	42	#if defined(CONFIG_SPL_BUILD)
072cefe0 HP	43	static const struct ddr_data ddr3_data = {
	44	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	45	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	46	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	47	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	48	};
2b1e2424	49
072cefe0 HP	50	static const struct cmd_control ddr3_cmd_ctrl_data = {
	51	.cmd0csratio = MT41K256M16HA125E_RATIO,
	52	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	53
	54	.cmd1csratio = MT41K256M16HA125E_RATIO,
	55	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	56
	57	.cmd2csratio = MT41K256M16HA125E_RATIO,
	58	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
	59	};
2b1e2424	60
072cefe0 HP	61	static struct emif_regs ddr3_emif_reg_data = {
	62	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	63	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	64	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	65	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	66	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	67	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	68	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
	69	};
	70
	71	static const struct ctrl_ioregs ddr3_ioregs = {
	72	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	73	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	74	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	75	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	76	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
	77	};
	78
2b1e2424 HS	79	#define OSC (V_OSCK / 1000000)
2b1e2424 HS	80	const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1};
072cefe0 HP	81
	82	void am33xx_spl_board_init(void)
	83	{
eaba7df7	84	int rc;
072cefe0 HP	85
	86	struct cm_perpll const cmper = (struct cm_perpll )CM_PER;
	87	struct cm_wkuppll const cmwkup = (struct cm_wkuppll )CM_WKUP;
	88	/*
	89	* enable additional clocks of modules which are accessed later from
	90	* VxWorks OS
	91	*/
	92	u32 *const clk_domains[] = { 0 };
	93
a4d79993	94	u32 *const clk_modules_xre1specific[] = {
072cefe0 HP	95	&cmwkup->wkup_adctscctrl,
	96	&cmper->spi1clkctrl,
	97	&cmper->dcan0clkctrl,
	98	&cmper->dcan1clkctrl,
	99	&cmper->epwmss0clkctrl,
	100	&cmper->epwmss1clkctrl,
	101	&cmper->epwmss2clkctrl,
cf630f28 HP	102	&cmper->lcdclkctrl,
cf630f28 HP	103	&cmper->lcdcclkstctrl,
072cefe0 HP	104	0
072cefe0 HP	105	};
a4d79993	106	do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
072cefe0	107	/* power-OFF LCD-Display */
eaba7df7 HS	108	if (gpio_request(LCD_PWR, "LCD_PWR") != 0)
	109	printf("cannot request gpio for LCD_PWR!\n");
	110	else if (gpio_direction_output(LCD_PWR, 0) != 0)
	111	printf("cannot set direction output on LCD_PWR!\n");
072cefe0 HP	112
072cefe0 HP	113	/* setup I2C */
2b5b2be5	114	enable_i2c_pin_mux();
072cefe0	115
eaba7df7	116	/* power-ON 3V3 via Resetcontroller */
1d260739 HS	117	rc = br_resetc_regset(RSTCTRL_CTRLREG,
1d260739 HS	118	RSTCTRL_FORCE_PWR_NEN \| RSTCTRL_CAN_STB);
eaba7df7	119	if (rc != 0)
1d260739	120	printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n");
072cefe0	121
a9484aa7	122	pmicsetup(0, 0);
072cefe0 HP	123	}
	124
	125	const struct dpll_params *get_dpll_ddr_params(void)
	126	{
	127	return &dpll_ddr3;
	128	}
	129
	130	void sdram_init(void)
	131	{
	132	config_ddr(400, &ddr3_ioregs,
	133	&ddr3_data,
	134	&ddr3_cmd_ctrl_data,
	135	&ddr3_emif_reg_data, 0);
	136	}
	137	#endif /* CONFIG_SPL_BUILD */
	138	/*
	139	* Basic board specific setup. Pinmux has been handled already.
	140	*/
	141	int board_init(void)
	142	{
1d260739 HS	143	/* request common used gpios */
	144	gpio_request(ESC_KEY, "boot-key");
	145
eaba7df7 HS	146	if (power_tps65217_init(0))
	147	printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n");
	148
072cefe0 HP	149	return 0;
	150	}
	151
	152	#ifdef CONFIG_BOARD_LATE_INIT
072cefe0	153
1d260739 HS	154	int board_boot_key(void)
	155	{
	156	return gpio_get_value(ESC_KEY);
	157	}
072cefe0	158
1d260739 HS	159	int board_late_init(void)
	160	{
	161	char othbootargs[128];
072cefe0	162
1d260739	163	br_resetc_bmode();
eaba7df7	164
91931f7e	165	/* setup othbootargs for bootvx-command (vxWorks bootline) */
ac36dc7d AG	166	snprintf(othbootargs, sizeof(othbootargs),
	167	"u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
	168	(u32)gd->relocaddr,
	169	(u32)env_get_ulong("vx_memtop", 16, gd->relocaddr),
	170	(u32)env_get_ulong("vx_romfsbase", 16, 0),
	171	(u32)env_get_ulong("vx_romfssize", 16, 0));
382bee57	172	env_set("othbootargs", othbootargs);
072cefe0 HP	173	/*
	174	* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
	175	* expect that vectors are there, original u-boot moves them to _start
	176	*/
	177	__asm__("ldr r0,=0x20000");
	178	__asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
	179
	180	return 0;
	181	}
	182	#endif /* CONFIG_BOARD_LATE_INIT */