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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
072cefe0 HP |
2 | /* |
3 | * board.c | |
4 | * | |
a4d79993 | 5 | * Board functions for B&R BRXRE1 Board |
072cefe0 | 6 | * |
4c302b9a | 7 | * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> |
072cefe0 HP |
8 | * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com |
9 | * | |
072cefe0 | 10 | */ |
d678a59d | 11 | #include <common.h> |
9eef56db | 12 | #include <env.h> |
072cefe0 | 13 | #include <errno.h> |
5255932f | 14 | #include <init.h> |
072cefe0 HP |
15 | #include <spl.h> |
16 | #include <asm/arch/cpu.h> | |
17 | #include <asm/arch/hardware.h> | |
18 | #include <asm/arch/omap.h> | |
19 | #include <asm/arch/ddr_defs.h> | |
20 | #include <asm/arch/clock.h> | |
21 | #include <asm/arch/gpio.h> | |
22 | #include <asm/arch/sys_proto.h> | |
23 | #include <asm/arch/mem.h> | |
401d1c4f | 24 | #include <asm/global_data.h> |
072cefe0 HP |
25 | #include <asm/io.h> |
26 | #include <asm/emif.h> | |
27 | #include <asm/gpio.h> | |
eaba7df7 | 28 | #include <dm.h> |
072cefe0 HP |
29 | #include <power/tps65217.h> |
30 | #include "../common/bur_common.h" | |
1d260739 | 31 | #include "../common/br_resetc.h" |
072cefe0 HP |
32 | |
33 | /* -------------------------------------------------------------------------*/ | |
34 | /* -- defines for used GPIO Hardware -- */ | |
2b1e2424 HS |
35 | #define ESC_KEY (0 + 19) |
36 | #define LCD_PWR (0 + 5) | |
072cefe0 | 37 | |
1d260739 HS |
38 | #define RSTCTRL_FORCE_PWR_NEN 0x04 |
39 | #define RSTCTRL_CAN_STB 0x40 | |
072cefe0 | 40 | |
a9642925 HP |
41 | DECLARE_GLOBAL_DATA_PTR; |
42 | ||
072cefe0 | 43 | #if defined(CONFIG_SPL_BUILD) |
072cefe0 HP |
44 | static const struct ddr_data ddr3_data = { |
45 | .datardsratio0 = MT41K256M16HA125E_RD_DQS, | |
46 | .datawdsratio0 = MT41K256M16HA125E_WR_DQS, | |
47 | .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, | |
48 | .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, | |
49 | }; | |
2b1e2424 | 50 | |
072cefe0 HP |
51 | static const struct cmd_control ddr3_cmd_ctrl_data = { |
52 | .cmd0csratio = MT41K256M16HA125E_RATIO, | |
53 | .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
54 | ||
55 | .cmd1csratio = MT41K256M16HA125E_RATIO, | |
56 | .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
57 | ||
58 | .cmd2csratio = MT41K256M16HA125E_RATIO, | |
59 | .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
60 | }; | |
2b1e2424 | 61 | |
072cefe0 HP |
62 | static struct emif_regs ddr3_emif_reg_data = { |
63 | .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, | |
64 | .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, | |
65 | .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, | |
66 | .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, | |
67 | .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, | |
68 | .zq_config = MT41K256M16HA125E_ZQ_CFG, | |
69 | .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, | |
70 | }; | |
71 | ||
72 | static const struct ctrl_ioregs ddr3_ioregs = { | |
73 | .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
74 | .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
75 | .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
76 | .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
77 | .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
78 | }; | |
79 | ||
2b1e2424 HS |
80 | #define OSC (V_OSCK / 1000000) |
81 | const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1}; | |
072cefe0 HP |
82 | |
83 | void am33xx_spl_board_init(void) | |
84 | { | |
eaba7df7 | 85 | int rc; |
072cefe0 HP |
86 | |
87 | struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; | |
88 | struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP; | |
89 | /* | |
90 | * enable additional clocks of modules which are accessed later from | |
91 | * VxWorks OS | |
92 | */ | |
93 | u32 *const clk_domains[] = { 0 }; | |
94 | ||
a4d79993 | 95 | u32 *const clk_modules_xre1specific[] = { |
072cefe0 HP |
96 | &cmwkup->wkup_adctscctrl, |
97 | &cmper->spi1clkctrl, | |
98 | &cmper->dcan0clkctrl, | |
99 | &cmper->dcan1clkctrl, | |
100 | &cmper->epwmss0clkctrl, | |
101 | &cmper->epwmss1clkctrl, | |
102 | &cmper->epwmss2clkctrl, | |
cf630f28 HP |
103 | &cmper->lcdclkctrl, |
104 | &cmper->lcdcclkstctrl, | |
072cefe0 HP |
105 | 0 |
106 | }; | |
a4d79993 | 107 | do_enable_clocks(clk_domains, clk_modules_xre1specific, 1); |
072cefe0 | 108 | /* power-OFF LCD-Display */ |
eaba7df7 HS |
109 | if (gpio_request(LCD_PWR, "LCD_PWR") != 0) |
110 | printf("cannot request gpio for LCD_PWR!\n"); | |
111 | else if (gpio_direction_output(LCD_PWR, 0) != 0) | |
112 | printf("cannot set direction output on LCD_PWR!\n"); | |
072cefe0 HP |
113 | |
114 | /* setup I2C */ | |
2b5b2be5 | 115 | enable_i2c_pin_mux(); |
072cefe0 | 116 | |
eaba7df7 | 117 | /* power-ON 3V3 via Resetcontroller */ |
1d260739 HS |
118 | rc = br_resetc_regset(RSTCTRL_CTRLREG, |
119 | RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB); | |
eaba7df7 | 120 | if (rc != 0) |
1d260739 | 121 | printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n"); |
072cefe0 | 122 | |
a9484aa7 | 123 | pmicsetup(0, 0); |
072cefe0 HP |
124 | } |
125 | ||
126 | const struct dpll_params *get_dpll_ddr_params(void) | |
127 | { | |
128 | return &dpll_ddr3; | |
129 | } | |
130 | ||
131 | void sdram_init(void) | |
132 | { | |
133 | config_ddr(400, &ddr3_ioregs, | |
134 | &ddr3_data, | |
135 | &ddr3_cmd_ctrl_data, | |
136 | &ddr3_emif_reg_data, 0); | |
137 | } | |
138 | #endif /* CONFIG_SPL_BUILD */ | |
139 | /* | |
140 | * Basic board specific setup. Pinmux has been handled already. | |
141 | */ | |
142 | int board_init(void) | |
143 | { | |
1d260739 HS |
144 | /* request common used gpios */ |
145 | gpio_request(ESC_KEY, "boot-key"); | |
146 | ||
eaba7df7 HS |
147 | if (power_tps65217_init(0)) |
148 | printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n"); | |
149 | ||
072cefe0 HP |
150 | return 0; |
151 | } | |
152 | ||
153 | #ifdef CONFIG_BOARD_LATE_INIT | |
072cefe0 | 154 | |
1d260739 HS |
155 | int board_boot_key(void) |
156 | { | |
157 | return gpio_get_value(ESC_KEY); | |
158 | } | |
072cefe0 | 159 | |
1d260739 HS |
160 | int board_late_init(void) |
161 | { | |
162 | char othbootargs[128]; | |
072cefe0 | 163 | |
1d260739 | 164 | br_resetc_bmode(); |
eaba7df7 | 165 | |
91931f7e | 166 | /* setup othbootargs for bootvx-command (vxWorks bootline) */ |
ac36dc7d AG |
167 | snprintf(othbootargs, sizeof(othbootargs), |
168 | "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", | |
169 | (u32)gd->relocaddr, | |
170 | (u32)env_get_ulong("vx_memtop", 16, gd->relocaddr), | |
171 | (u32)env_get_ulong("vx_romfsbase", 16, 0), | |
172 | (u32)env_get_ulong("vx_romfssize", 16, 0)); | |
382bee57 | 173 | env_set("othbootargs", othbootargs); |
072cefe0 HP |
174 | /* |
175 | * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does | |
176 | * expect that vectors are there, original u-boot moves them to _start | |
177 | */ | |
178 | __asm__("ldr r0,=0x20000"); | |
179 | __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */ | |
180 | ||
181 | return 0; | |
182 | } | |
183 | #endif /* CONFIG_BOARD_LATE_INIT */ |