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Merge git://git.denx.de/u-boot-sunxi
[people/ms/u-boot.git] / board / CZ.NIC / turris_omnia / turris_omnia.c
CommitLineData
b6ee860b
MB		 1/*
2 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
3 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
4 *
5 * Derived from the code for
6 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <i2c.h>
13#include <miiphy.h>
14#include <netdev.h>
15#include <asm/io.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
18#include <dm/uclass.h>
19#include <fdt_support.h>
20#include <time.h>
21
22#ifdef CONFIG_ATSHA204A
23# include <atsha204a-i2c.h>
24#endif
25
26#ifdef CONFIG_WDT_ORION
27# include <wdt.h>
28#endif
29
30#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
31#include <../serdes/a38x/high_speed_env_spec.h>
32
33DECLARE_GLOBAL_DATA_PTR;
34
35#define OMNIA_I2C_EEPROM_DM_NAME "i2c@0"
36#define OMNIA_I2C_EEPROM 0x54
37#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0
38#define OMNIA_I2C_EEPROM_ADDRLEN 2
39#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
40
41#define OMNIA_I2C_MCU_DM_NAME "i2c@0"
42#define OMNIA_I2C_MCU_ADDR_STATUS 0x1
43#define OMNIA_I2C_MCU_SATA 0x20
44#define OMNIA_I2C_MCU_CARDDET 0x10
45#define OMNIA_I2C_MCU 0x2a
46#define OMNIA_I2C_MCU_WDT_ADDR 0x0b
47
48#define OMNIA_ATSHA204_OTP_VERSION 0
49#define OMNIA_ATSHA204_OTP_SERIAL 1
50#define OMNIA_ATSHA204_OTP_MAC0 3
51#define OMNIA_ATSHA204_OTP_MAC1 4
52
53#define MVTWSI_ARMADA_DEBUG_REG 0x8c
54
55/*
56 * Those values and defines are taken from the Marvell U-Boot version
57 * "u-boot-2013.01-2014_T3.0"
58 */
59#define OMNIA_GPP_OUT_ENA_LOW \
60 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
61 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
62 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
63#define OMNIA_GPP_OUT_ENA_MID \
64 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
65 BIT(16) | BIT(17) | BIT(18)))
66
67#define OMNIA_GPP_OUT_VAL_LOW 0x0
68#define OMNIA_GPP_OUT_VAL_MID 0x0
69#define OMNIA_GPP_POL_LOW 0x0
70#define OMNIA_GPP_POL_MID 0x0
71
72static struct serdes_map board_serdes_map_pex[] = {
73 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
74 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
75 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
76 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
77 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
78 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
79};
80
81static struct serdes_map board_serdes_map_sata[] = {
82 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
83 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
84 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
85 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
87 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
88};
89
90static bool omnia_detect_sata(void)
91{
92 struct udevice *bus, *dev;
8daa3468 93 int ret, retry = 3;
b6ee860b
MB		 94 u16 mode;
95
96 puts("SERDES0 card detect: ");
97
98 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
99 puts("Cannot find MCU bus!\n");
100 return false;
101 }
102
103 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
104 if (ret) {
105 puts("Cannot get MCU chip!\n");
106 return false;
107 }
108
8daa3468
MB		 109 for (; retry > 0; --retry) {
110 ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2);
111 if (!ret)
112 break;
113 }
114
115 if (!retry) {
b6ee860b
MB		 116 puts("I2C read failed! Default PEX\n");
117 return false;
118 }
119
120 if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
121 puts("NONE\n");
122 return false;
123 }
124
125 if (mode & OMNIA_I2C_MCU_SATA) {
126 puts("SATA\n");
127 return true;
128 } else {
129 puts("PEX\n");
130 return false;
131 }
132}
133
134int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
135{
136 if (omnia_detect_sata()) {
137 *serdes_map_array = board_serdes_map_sata;
138 *count = ARRAY_SIZE(board_serdes_map_sata);
139 } else {
140 *serdes_map_array = board_serdes_map_pex;
141 *count = ARRAY_SIZE(board_serdes_map_pex);
142 }
143
144 return 0;
145}
146
147struct omnia_eeprom {
148 u32 magic;
149 u32 ramsize;
150 char region[4];
151 u32 crc;
152};
153
154static bool omnia_read_eeprom(struct omnia_eeprom *oep)
155{
156 struct udevice *bus, *dev;
157 int ret, crc, retry = 3;
158
159 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) {
160 puts("Cannot find EEPROM bus\n");
161 return false;
162 }
163
164 ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev);
165 if (ret) {
166 puts("Cannot get EEPROM chip\n");
167 return false;
168 }
169
170 for (; retry > 0; --retry) {
171 ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom));
172 if (ret)
173 continue;
174
175 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
176 puts("I2C EEPROM missing magic number!\n");
177 continue;
178 }
179
180 crc = crc32(0, (unsigned char *) oep,
181 sizeof(struct omnia_eeprom) - 4);
182 if (crc == oep->crc) {
183 break;
184 } else {
185 printf("CRC of EEPROM memory config failed! "
186 "calc=0x%04x saved=0x%04x\n", crc, oep->crc);
187 }
188 }
189
190 if (!retry) {
191 puts("I2C EEPROM read failed!\n");
192 return false;
193 }
194
195 return true;
196}
197
198/*
199 * Define the DDR layout / topology here in the board file. This will
200 * be used by the DDR3 init code in the SPL U-Boot version to configure
201 * the DDR3 controller.
202 */
203static struct hws_topology_map board_topology_map_1g = {
204 0x1, /* active interfaces */
205 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
206 { { { {0x1, 0, 0, 0},
207 {0x1, 0, 0, 0},
208 {0x1, 0, 0, 0},
209 {0x1, 0, 0, 0},
210 {0x1, 0, 0, 0} },
211 SPEED_BIN_DDR_1600K, /* speed_bin */
212 BUS_WIDTH_16, /* memory_width */
213 MEM_4G, /* mem_size */
214 DDR_FREQ_800, /* frequency */
01c541e0 215 0, 0, /* cas_wl cas_l */
b6ee860b
MB		 216 HWS_TEMP_NORMAL, /* temperature */
217 HWS_TIM_2T} }, /* timing (force 2t) */
218 5, /* Num Of Bus Per Interface*/
219 BUS_MASK_32BIT /* Busses mask */
220};
221
222static struct hws_topology_map board_topology_map_2g = {
223 0x1, /* active interfaces */
224 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
225 { { { {0x1, 0, 0, 0},
226 {0x1, 0, 0, 0},
227 {0x1, 0, 0, 0},
228 {0x1, 0, 0, 0},
229 {0x1, 0, 0, 0} },
230 SPEED_BIN_DDR_1600K, /* speed_bin */
231 BUS_WIDTH_16, /* memory_width */
232 MEM_8G, /* mem_size */
233 DDR_FREQ_800, /* frequency */
01c541e0 234 0, 0, /* cas_wl cas_l */
b6ee860b
MB		 235 HWS_TEMP_NORMAL, /* temperature */
236 HWS_TIM_2T} }, /* timing (force 2t) */
237 5, /* Num Of Bus Per Interface*/
238 BUS_MASK_32BIT /* Busses mask */
239};
240
241struct hws_topology_map *ddr3_get_topology_map(void)
242{
243 static int mem = 0;
244 struct omnia_eeprom oep;
245
246 /* Get the board config from EEPROM */
247 if (mem == 0) {
248 if(!omnia_read_eeprom(&oep))
249 goto out;
250
251 printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
252
253 if (oep.ramsize == 0x2)
254 mem = 2;
255 else
256 mem = 1;
257 }
258
259out:
260 /* Hardcoded fallback */
261 if (mem == 0) {
262 puts("WARNING: Memory config from EEPROM read failed.\n");
263 puts("Falling back to default 1GiB map.\n");
264 mem = 1;
265 }
266
267 /* Return the board topology as defined in the board code */
268 if (mem == 1)
269 return &board_topology_map_1g;
270 if (mem == 2)
271 return &board_topology_map_2g;
272
273 return &board_topology_map_1g;
274}
275
276#ifndef CONFIG_SPL_BUILD
277static int set_regdomain(void)
278{
279 struct omnia_eeprom oep;
280 char rd[3] = {' ', ' ', 0};
281
282 if (omnia_read_eeprom(&oep))
283 memcpy(rd, &oep.region, 2);
284 else
285 puts("EEPROM regdomain read failed.\n");
286
287 printf("Regdomain set to %s\n", rd);
382bee57 288 return env_set("regdomain", rd);
b6ee860b
MB		 289}
290#endif
291
292int board_early_init_f(void)
293{
294 u32 i2c_debug_reg;
295
296 /* Configure MPP */
297 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
298 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
299 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
300 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
301 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
302 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
303 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
304 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
305
306 /* Set GPP Out value */
307 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
308 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
309
310 /* Set GPP Polarity */
311 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
312 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
313
314 /* Set GPP Out Enable */
315 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
316 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
317
318 /* Disable I2C debug mode blocking 0x64 I2C address */
319 i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
320 i2c_debug_reg &= ~(1<<18);
321 writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
322
323 return 0;
324}
325
326#ifndef CONFIG_SPL_BUILD
327static bool disable_mcu_watchdog(void)
328{
329 struct udevice *bus, *dev;
330 int ret, retry = 3;
331 uchar buf[1] = {0x0};
332
333 if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) {
334 puts("Cannot find MCU bus! Can not disable MCU WDT.\n");
335 return false;
336 }
337
338 ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
339 if (ret) {
340 puts("Cannot get MCU chip! Can not disable MCU WDT.\n");
341 return false;
342 }
343
344 for (; retry > 0; --retry)
345 if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1))
346 break;
347
348 if (retry <= 0) {
349 puts("I2C MCU watchdog failed to disable!\n");
350 return false;
351 }
352
353 return true;
354}
355#endif
356
357#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
358static struct udevice *watchdog_dev = NULL;
359#endif
360
361int board_init(void)
362{
363 /* adress of boot parameters */
364 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
365
366#ifndef CONFIG_SPL_BUILD
367# ifdef CONFIG_WDT_ORION
368 if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
369 puts("Cannot find Armada 385 watchdog!\n");
370 } else {
371 puts("Enabling Armada 385 watchdog.\n");
372 wdt_start(watchdog_dev, (u32) 25000000 * 120, 0);
373 }
374# endif
375
376 if (disable_mcu_watchdog())
377 puts("Disabled MCU startup watchdog.\n");
378
379 set_regdomain();
380#endif
381
382 return 0;
383}
384
385#ifdef CONFIG_WATCHDOG
386/* Called by macro WATCHDOG_RESET */
387void watchdog_reset(void)
388{
389# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION)
390 static ulong next_reset = 0;
391 ulong now;
392
393 if (!watchdog_dev)
394 return;
395
396 now = timer_get_us();
397
398 /* Do not reset the watchdog too often */
399 if (now > next_reset) {
400 wdt_reset(watchdog_dev);
401 next_reset = now + 1000;
402 }
403# endif
404}
405#endif
406
407int board_late_init(void)
408{
409#ifndef CONFIG_SPL_BUILD
410 set_regdomain();
411#endif
412
413 return 0;
414}
415
416#ifdef CONFIG_ATSHA204A
417static struct udevice *get_atsha204a_dev(void)
418{
419 static struct udevice *dev = NULL;
420
421 if (dev != NULL)
422 return dev;
423
424 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
425 puts("Cannot find ATSHA204A on I2C bus!\n");
426 dev = NULL;
427 }
428
429 return dev;
430}
431#endif
432
433int checkboard(void)
434{
435 u32 version_num, serial_num;
436 int err = 1;
437
438#ifdef CONFIG_ATSHA204A
439 struct udevice *dev = get_atsha204a_dev();
440
441 if (dev) {
442 err = atsha204a_wakeup(dev);
443 if (err)
444 goto out;
445
446 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
447 OMNIA_ATSHA204_OTP_VERSION,
448 (u8 *) &version_num);
449 if (err)
450 goto out;
451
452 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
453 OMNIA_ATSHA204_OTP_SERIAL,
454 (u8 *) &serial_num);
455 if (err)
456 goto out;
457
458 atsha204a_sleep(dev);
459 }
460
461out:
462#endif
463
464 if (err)
465 printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
466 else
467 printf("Board: Turris Omnia SNL %08X%08X\n",
468 be32_to_cpu(version_num), be32_to_cpu(serial_num));
469
470 return 0;
471}
472
473static void increment_mac(u8 *mac)
474{
475 int i;
476
477 for (i = 5; i >= 3; i--) {
478 mac[i] += 1;
479 if (mac[i])
480 break;
481 }
482}
483
484int misc_init_r(void)
485{
486#ifdef CONFIG_ATSHA204A
487 int err;
488 struct udevice *dev = get_atsha204a_dev();
489 u8 mac0[4], mac1[4], mac[6];
490
491 if (!dev)
492 goto out;
493
494 err = atsha204a_wakeup(dev);
495 if (err)
496 goto out;
497
498 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
499 OMNIA_ATSHA204_OTP_MAC0, mac0);
500 if (err)
501 goto out;
502
503 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
504 OMNIA_ATSHA204_OTP_MAC1, mac1);
505 if (err)
506 goto out;
507
508 atsha204a_sleep(dev);
509
510 mac[0] = mac0[1];
511 mac[1] = mac0[2];
512 mac[2] = mac0[3];
513 mac[3] = mac1[1];
514 mac[4] = mac1[2];
515 mac[5] = mac1[3];
516
517 if (is_valid_ethaddr(mac))
fd1e959e 518 eth_env_set_enetaddr("ethaddr", mac);
b6ee860b
MB		 519
520 increment_mac(mac);
521
522 if (is_valid_ethaddr(mac))
fd1e959e 523 eth_env_set_enetaddr("eth1addr", mac);
b6ee860b
MB		 524
525 increment_mac(mac);
526
527 if (is_valid_ethaddr(mac))
fd1e959e 528 eth_env_set_enetaddr("eth2addr", mac);
b6ee860b
MB		 529
530out:
531#endif
532
533 return 0;
534}
535
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