[people/ms/u-boot.git] / board / CarMediaLab / flea3 / flea3.c

/*
 * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
 *
 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>

#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
#endif

#define CCM_CCMR_CONFIG		0x003F4208

#define ESDCTL_DDR2_CONFIG	0x007FFC3F
#define ESDCTL_0x92220000	0x92220000
#define ESDCTL_0xA2220000	0xA2220000
#define ESDCTL_0xB2220000	0xB2220000
#define ESDCTL_0x82228080	0x82228080
#define ESDCTL_DDR2_EMR2	0x04000000
#define ESDCTL_DDR2_EMR3	0x06000000
#define ESDCTL_PRECHARGE	0x00000400
#define ESDCTL_DDR2_EN_DLL	0x02000400
#define ESDCTL_DDR2_RESET_DLL	0x00000333
#define ESDCTL_DDR2_MR		0x00000233
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
#define ESDCTL_DELAY_LINE5	0x00F49F00

static inline void dram_wait(unsigned int count)
{
	volatile unsigned int wait = count;

	while (wait--)
		;
}

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
		PHYS_SDRAM_1_SIZE);

	return 0;
}

static void board_setup_sdram_bank(u32 start_address)

{
	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
	u32 *cfg_reg, *ctl_reg;
	u32 val;

	switch (start_address) {
	case CSD0_BASE_ADDR:
		cfg_reg = &esdc->esdcfg0;
		ctl_reg = &esdc->esdctl0;
		break;
	case CSD1_BASE_ADDR:
		cfg_reg = &esdc->esdcfg1;
		ctl_reg = &esdc->esdctl1;
		break;
	default:
		return;
	}

	/* Initialize MISC register for DDR2 */
	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
	writel(val, &esdc->esdmisc);
	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
	writel(val, &esdc->esdmisc);

	/*
	 * according to DDR2 specs, wait a while before
	 * the PRECHARGE_ALL command
	 */
	dram_wait(0x20000);

	/* Load DDR2 config and timing */
	writel(ESDCTL_DDR2_CONFIG, cfg_reg);

	/* Precharge ALL */
	writel(ESDCTL_0x92220000,
		ctl_reg);
	writel(0xda, start_address + ESDCTL_PRECHARGE);

	/* Load mode */
	writel(ESDCTL_0xB2220000,
		ctl_reg);
	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */

	/* Precharge ALL */
	writel(ESDCTL_0x92220000,
		ctl_reg);
	writel(0xda, start_address + ESDCTL_PRECHARGE);

	/* Set mode auto refresh : at least two refresh are required */
	writel(ESDCTL_0xA2220000,
		ctl_reg);
	writel(0xda, start_address);
	writel(0xda, start_address);

	writel(ESDCTL_0xB2220000,
		ctl_reg);
	writeb(0xda, start_address + ESDCTL_DDR2_MR);
	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);

	/* OCD mode exit */
	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */

	/* Set normal mode */
	writel(ESDCTL_0x82228080,
		ctl_reg);

	dram_wait(0x20000);

	/* Do not set delay lines, only for MDDR */
}

static void board_setup_sdram(void)
{
	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;

	/* Initialize with default values both CSD0/1 */
	writel(0x2000, &esdc->esdctl0);
	writel(0x2000, &esdc->esdctl1);

	board_setup_sdram_bank(CSD0_BASE_ADDR);
}

static void setup_iomux_uart3(void)
{
	static const iomux_v3_cfg_t uart3_pads[] = {
		MX35_PAD_RTS2__UART3_RXD_MUX,
		MX35_PAD_CTS2__UART3_TXD_MUX,
	};

	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}

#define I2C_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)

static void setup_iomux_i2c(void)
{
	static const iomux_v3_cfg_t i2c_pads[] = {
		NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),

		NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
		NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
	};

	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}


static void setup_iomux_spi(void)
{
	static const iomux_v3_cfg_t spi_pads[] = {
		MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
		MX35_PAD_CSPI1_MISO__CSPI1_MISO,
		MX35_PAD_CSPI1_SS0__CSPI1_SS0,
		MX35_PAD_CSPI1_SS1__CSPI1_SS1,
		MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	};

	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
		MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
		MX35_PAD_FEC_RX_DV__FEC_RX_DV,
		MX35_PAD_FEC_COL__FEC_COL,
		MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
		MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
		MX35_PAD_FEC_TX_EN__FEC_TX_EN,
		MX35_PAD_FEC_MDC__FEC_MDC,
		MX35_PAD_FEC_MDIO__FEC_MDIO,
		MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
		MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
		MX35_PAD_FEC_CRS__FEC_CRS,
		MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
		MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
		MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	};

	/* setup pins for FEC */
	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

int board_early_init_f(void)
{
	struct ccm_regs *ccm =
		(struct ccm_regs *)IMX_CCM_BASE;

	/* setup GPIO3_1 to set HighVCore signal */
	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
	gpio_direction_output(65, 1);

	/* initialize PLL and clock configuration */
	writel(CCM_CCMR_CONFIG, &ccm->ccmr);

	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
	writel(CCM_PPLL_300_HZ, &ccm->ppctl);

	/* Set the core to run at 532 Mhz */
	writel(0x00001000, &ccm->pdr0);

	/* Set-up RAM */
	board_setup_sdram();

	/* enable clocks */
	writel(readl(&ccm->cgr0) |
		MXC_CCM_CGR0_EMI_MASK |
		MXC_CCM_CGR0_EDIO_MASK |
		MXC_CCM_CGR0_EPIT1_MASK,
		&ccm->cgr0);

	writel(readl(&ccm->cgr1) |
		MXC_CCM_CGR1_FEC_MASK |
		MXC_CCM_CGR1_GPIO1_MASK |
		MXC_CCM_CGR1_GPIO2_MASK |
		MXC_CCM_CGR1_GPIO3_MASK |
		MXC_CCM_CGR1_I2C1_MASK |
		MXC_CCM_CGR1_I2C2_MASK |
		MXC_CCM_CGR1_I2C3_MASK,
		&ccm->cgr1);

	/* Set-up NAND */
	__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);

	/* Set pinmux for the required peripherals */
	setup_iomux_uart3();
	setup_iomux_i2c();
	setup_iomux_fec();
	setup_iomux_spi();

	return 0;
}

int board_init(void)
{
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

u32 get_board_rev(void)
{
	int rev = 0;

	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
Commit	Line	Data
deb53483 SB	1	/*
	2	* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
	3	*
	4	* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
	5	*
	6	* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/io.h>
	29	#include <asm/errno.h>
	30	#include <asm/arch/imx-regs.h>
	31	#include <asm/arch/crm_regs.h>
686e1448	32	#include <asm/arch/iomux-mx35.h>
deb53483 SB	33	#include <i2c.h>
	34	#include <linux/types.h>
	35	#include <asm/gpio.h>
	36	#include <asm/arch/sys_proto.h>
	37	#include <netdev.h>
	38
	39	#ifndef CONFIG_BOARD_EARLY_INIT_F
	40	#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
	41	#endif
	42
	43	#define CCM_CCMR_CONFIG 0x003F4208
	44
	45	#define ESDCTL_DDR2_CONFIG 0x007FFC3F
	46	#define ESDCTL_0x92220000 0x92220000
	47	#define ESDCTL_0xA2220000 0xA2220000
	48	#define ESDCTL_0xB2220000 0xB2220000
	49	#define ESDCTL_0x82228080 0x82228080
	50	#define ESDCTL_DDR2_EMR2 0x04000000
	51	#define ESDCTL_DDR2_EMR3 0x06000000
	52	#define ESDCTL_PRECHARGE 0x00000400
	53	#define ESDCTL_DDR2_EN_DLL 0x02000400
	54	#define ESDCTL_DDR2_RESET_DLL 0x00000333
	55	#define ESDCTL_DDR2_MR 0x00000233
	56	#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
	57	#define ESDCTL_DELAY_LINE5 0x00F49F00
	58
	59	static inline void dram_wait(unsigned int count)
	60	{
	61	volatile unsigned int wait = count;
	62
	63	while (wait--)
	64	;
	65	}
	66
	67	DECLARE_GLOBAL_DATA_PTR;
	68
	69	int dram_init(void)
	70	{
	71	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
	72	PHYS_SDRAM_1_SIZE);
	73
	74	return 0;
	75	}
	76
	77	static void board_setup_sdram_bank(u32 start_address)
	78
	79	{
	80	struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
	81	u32 cfg_reg, ctl_reg;
	82	u32 val;
	83
	84	switch (start_address) {
	85	case CSD0_BASE_ADDR:
	86	cfg_reg = &esdc->esdcfg0;
	87	ctl_reg = &esdc->esdctl0;
	88	break;
	89	case CSD1_BASE_ADDR:
	90	cfg_reg = &esdc->esdcfg1;
	91	ctl_reg = &esdc->esdctl1;
	92	break;
	93	default:
	94	return;
	95	}
	96
97	/* Initialize MISC register for DDR2 */
98	val = ESDC_MISC_RST \| ESDC_MISC_MDDR_EN \| ESDC_MISC_MDDR_DL_RST \|
99	ESDC_MISC_DDR_EN \| ESDC_MISC_DDR2_EN;
100	writel(val, &esdc->esdmisc);
101	val &= ~(ESDC_MISC_RST \| ESDC_MISC_MDDR_DL_RST);
102	writel(val, &esdc->esdmisc);
103
104	/*
105	* according to DDR2 specs, wait a while before
106	* the PRECHARGE_ALL command
107	*/
108	dram_wait(0x20000);
109
110	/* Load DDR2 config and timing */
111	writel(ESDCTL_DDR2_CONFIG, cfg_reg);
112
113	/* Precharge ALL */
114	writel(ESDCTL_0x92220000,
115	ctl_reg);
116	writel(0xda, start_address + ESDCTL_PRECHARGE);
117
118	/* Load mode */
119	writel(ESDCTL_0xB2220000,
120	ctl_reg);
121	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
122	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
123	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
124	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
125
126	/* Precharge ALL */
127	writel(ESDCTL_0x92220000,
128	ctl_reg);
129	writel(0xda, start_address + ESDCTL_PRECHARGE);
130
131	/* Set mode auto refresh : at least two refresh are required */
132	writel(ESDCTL_0xA2220000,
133	ctl_reg);
134	writel(0xda, start_address);
135	writel(0xda, start_address);
136
137	writel(ESDCTL_0xB2220000,
138	ctl_reg);
139	writeb(0xda, start_address + ESDCTL_DDR2_MR);
140	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
141
142	/* OCD mode exit */
143	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
144
145	/* Set normal mode */
146	writel(ESDCTL_0x82228080,
147	ctl_reg);
148
149	dram_wait(0x20000);
150
151	/* Do not set delay lines, only for MDDR */
152	}
153
154	static void board_setup_sdram(void)
155	{
156	struct esdc_regs esdc = (struct esdc_regs )ESDCTL_BASE_ADDR;
157
158	/* Initialize with default values both CSD0/1 */
159	writel(0x2000, &esdc->esdctl0);
160	writel(0x2000, &esdc->esdctl1);
161
fda241d5	162	board_setup_sdram_bank(CSD0_BASE_ADDR);
deb53483 SB	163	}
	164
	165	static void setup_iomux_uart3(void)
	166	{
686e1448 BT	167	static const iomux_v3_cfg_t uart3_pads[] = {
	168	MX35_PAD_RTS2__UART3_RXD_MUX,
	169	MX35_PAD_CTS2__UART3_TXD_MUX,
	170	};
	171
	172	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
deb53483 SB	173	}
deb53483 SB	174
686e1448 BT	175	#define I2C_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_100K_DOWN \| PAD_CTL_ODE)
686e1448 BT	176
deb53483 SB	177	static void setup_iomux_i2c(void)
deb53483 SB	178	{
686e1448 BT	179	static const iomux_v3_cfg_t i2c_pads[] = {
	180	NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
	181	NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
deb53483	182
686e1448 BT	183	NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
	184	NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
	185	};
deb53483	186
686e1448	187	imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
deb53483 SB	188	}
	189
	190
	191	static void setup_iomux_spi(void)
	192	{
686e1448 BT	193	static const iomux_v3_cfg_t spi_pads[] = {
	194	MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
	195	MX35_PAD_CSPI1_MISO__CSPI1_MISO,
	196	MX35_PAD_CSPI1_SS0__CSPI1_SS0,
	197	MX35_PAD_CSPI1_SS1__CSPI1_SS1,
	198	MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
	199	};
	200
	201	imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
deb53483 SB	202	}
	203
	204	static void setup_iomux_fec(void)
	205	{
686e1448 BT	206	static const iomux_v3_cfg_t fec_pads[] = {
	207	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	208	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	209	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	210	MX35_PAD_FEC_COL__FEC_COL,
	211	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	212	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	213	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	214	MX35_PAD_FEC_MDC__FEC_MDC,
	215	MX35_PAD_FEC_MDIO__FEC_MDIO,
	216	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	217	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	218	MX35_PAD_FEC_CRS__FEC_CRS,
	219	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	220	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	221	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	222	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	223	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	224	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	225	};
deb53483	226
686e1448 BT	227	/* setup pins for FEC */
686e1448 BT	228	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
deb53483 SB	229	}
	230
	231	int board_early_init_f(void)
	232	{
	233	struct ccm_regs *ccm =
	234	(struct ccm_regs *)IMX_CCM_BASE;
	235
	236	/* setup GPIO3_1 to set HighVCore signal */
686e1448	237	imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
deb53483 SB	238	gpio_direction_output(65, 1);
	239
	240	/* initialize PLL and clock configuration */
	241	writel(CCM_CCMR_CONFIG, &ccm->ccmr);
	242
	243	writel(CCM_MPLL_532_HZ, &ccm->mpctl);
	244	writel(CCM_PPLL_300_HZ, &ccm->ppctl);
	245
	246	/* Set the core to run at 532 Mhz */
	247	writel(0x00001000, &ccm->pdr0);
	248
	249	/* Set-up RAM */
	250	board_setup_sdram();
	251
	252	/* enable clocks */
	253	writel(readl(&ccm->cgr0) \|
	254	MXC_CCM_CGR0_EMI_MASK \|
34a31bf5	255	MXC_CCM_CGR0_EDIO_MASK \|
deb53483 SB	256	MXC_CCM_CGR0_EPIT1_MASK,
	257	&ccm->cgr0);
	258
	259	writel(readl(&ccm->cgr1) \|
	260	MXC_CCM_CGR1_FEC_MASK \|
	261	MXC_CCM_CGR1_GPIO1_MASK \|
	262	MXC_CCM_CGR1_GPIO2_MASK \|
	263	MXC_CCM_CGR1_GPIO3_MASK \|
	264	MXC_CCM_CGR1_I2C1_MASK \|
	265	MXC_CCM_CGR1_I2C2_MASK \|
	266	MXC_CCM_CGR1_I2C3_MASK,
	267	&ccm->cgr1);
	268
	269	/* Set-up NAND */
	270	__raw_writel(readl(&ccm->rcsr) \| MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
	271
	272	/* Set pinmux for the required peripherals */
	273	setup_iomux_uart3();
	274	setup_iomux_i2c();
	275	setup_iomux_fec();
	276	setup_iomux_spi();
	277
	278	return 0;
	279	}
	280
	281	int board_init(void)
	282	{
	283	/* address of boot parameters */
	284	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	285
	286	return 0;
	287	}
	288
	289	u32 get_board_rev(void)
	290	{
	291	int rev = 0;
	292
	293	return (get_cpu_rev() & ~(0xF << 8)) \| (rev & 0xF) << 8;
	294	}