[people/ms/u-boot.git] / board / LEOX / elpt860 / elpt860.c

/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
**   for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
** This program is free software; you can redistribute it and/or
** modify it under the terms of the GNU General Public License as
** published by the Free Software Foundation; either version 2 of
** the License, or (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program; if not, write to the Free Software
** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
** MA 02111-1307 USA
**
**=====================================================================
*/

/*
** Note 1: In this file, you have to provide the following functions:
** ------
**              int             board_early_init_f(void)
**              int             checkboard(void)
**              phys_size_t     initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
**              void            reset_phy(void)
** called from 'board_init_r()' into 'common/board.c'
*/

#include <common.h>
#include <mpc8xx.h>

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint init_sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
	0xFFFFFC04,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
};

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	0xFF0FFC00,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
	_NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
};

/* ------------------------------------------------------------------------- */

#define CONFIG_SYS_PC4    0x0800

#define CONFIG_SYS_DS1    CONFIG_SYS_PC4

/*
 * Very early board init code (fpga boot, etc.)
 */
int board_early_init_f (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/*
	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
	 */
	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */

	return (0);		/* success */
}

/*
 * Check Board Identity:
 *
 * Test ELPT860 ID string
 *
 * Return 1 if no second DRAM bank, otherwise returns 0
 */

int checkboard (void)
{
	char *s = getenv ("serial#");

	if (!s || strncmp (s, "ELPT860", 7))
		printf ("### No HW ID - assuming ELPT860\n");

	return (0);		/* success */
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;

	/*
	 * This sequence initializes SDRAM chips on ELPT860 board
	 */
	upmconfig (UPMA, (uint *) init_sdram_table,
		   sizeof (init_sdram_table) / sizeof (uint));

	memctl->memc_mptpr = 0x0200;
	memctl->memc_mamr = 0x18002111;

	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;

	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;

	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
	udelay (1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);

	if (size8 < size9) {	/* leave configuration at 9 columns       */
		size_b0 = size9;
		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
	} else {		/* back to 8 columns                      */

		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
		udelay (500);
		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	}

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if (size_b0 < 0x02000000) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping: map bigger bank first
	 */
	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	{
		unsigned long reg;

		/* adjust refresh rate depending on SDRAM type, one bank */
		reg = memctl->memc_mptpr;
		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
		memctl->memc_mptpr = reg;
	}

	udelay (10000);

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int
dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size (base, maxsize));
}

/* ------------------------------------------------------------------------- */

#define CONFIG_SYS_PA1     0x4000
#define CONFIG_SYS_PA2     0x2000

#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)

void reset_phy (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/*
	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
	 *                                          and no AUI loopback
	 */
	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
}
Commit	Line	Data
3bac3513 WD	1	/*
	2	**=====================================================================
	3	**
	4	** Copyright (C) 2000, 2001, 2002, 2003
	5	** The LEOX team <team@leox.org>, http://www.leox.org
	6	**
	7	** LEOX.org is about the development of free hardware and software resources
	8	** for system on chip.
	9	**
	10	** Description: U-Boot port on the LEOX's ELPT860 CPU board
	11	** ~~~~~~~~~~~
	12	**
	13	**=====================================================================
	14	**
	15	** This program is free software; you can redistribute it and/or
	16	** modify it under the terms of the GNU General Public License as
	17	** published by the Free Software Foundation; either version 2 of
	18	** the License, or (at your option) any later version.
	19	**
	20	** This program is distributed in the hope that it will be useful,
	21	** but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	** GNU General Public License for more details.
	24	**
	25	** You should have received a copy of the GNU General Public License
	26	** along with this program; if not, write to the Free Software
	27	** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	** MA 02111-1307 USA
	29	**
	30	**=====================================================================
	31	*/
	32
	33	/*
	34	** Note 1: In this file, you have to provide the following functions:
	35	** ------
c837dcb1	36	** int board_early_init_f(void)
3bac3513	37	** int checkboard(void)
9973e3c6	38	** phys_size_t initdram(int board_type)
3bac3513 WD	39	** called from 'board_init_f()' into 'common/board.c'
	40	**
	41	** void reset_phy(void)
	42	** called from 'board_init_r()' into 'common/board.c'
	43	*/
	44
	45	#include <common.h>
	46	#include <mpc8xx.h>
	47
	48	/* ------------------------------------------------------------------------- */
	49
	50	static long int dram_size (long int, long int *, long int);
	51
	52	/* ------------------------------------------------------------------------- */
	53
	54	#define _NOT_USED_ 0xFFFFFFFF
	55
c83bf6a2 WD	56	const uint init_sdram_table[] = {
	57	/*
	58	* Single Read. (Offset 0 in UPMA RAM)
	59	*/
	60	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
	61	0xFFFFFC04, /* last */
	62	/*
	63	* SDRAM Initialization (offset 5 in UPMA RAM)
	64	*
	65	* This is no UPM entry point. The following definition uses
	66	* the remaining space to establish an initialization
	67	* sequence, which is executed by a RUN command.
	68	*
	69	*/
	70	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
	71	/*
	72	* Burst Read. (Offset 8 in UPMA RAM)
	73	*/
	74	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	75	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	76	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	77	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
	78	/*
	79	* Single Write. (Offset 18 in UPMA RAM)
	80	*/
	81	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
	82	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
	83	/*
	84	* Burst Write. (Offset 20 in UPMA RAM)
	85	*/
	86	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	87	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	88	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
	89	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
3bac3513 WD	90	};
3bac3513 WD	91
c83bf6a2 WD	92	const uint sdram_table[] = {
	93	/*
	94	* Single Read. (Offset 0 in UPMA RAM)
	95	*/
	96	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	97	0xFF0FFC00, /* last */
	98	/*
	99	* SDRAM Initialization (offset 5 in UPMA RAM)
	100	*
	101	* This is no UPM entry point. The following definition uses
	102	* the remaining space to establish an initialization
	103	* sequence, which is executed by a RUN command.
	104	*
	105	*/
	106	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
	107	/*
	108	* Burst Read. (Offset 8 in UPMA RAM)
	109	*/
	110	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	111	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
	112	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	113	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	114	/*
	115	* Single Write. (Offset 18 in UPMA RAM)
	116	*/
	117	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
	118	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
	119	_NOT_USED_,
	120	/*
	121	* Burst Write. (Offset 20 in UPMA RAM)
	122	*/
	123	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
	124	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
	125	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	126	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	127	/*
	128	* Refresh (Offset 30 in UPMA RAM)
	129	*/
	130	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	131	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
	132	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	133	/*
	134	* Exception. (Offset 3c in UPMA RAM)
	135	*/
	136	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
3bac3513 WD	137	};
	138
	139	/* ------------------------------------------------------------------------- */
	140
6d0f6bcf	141	#define CONFIG_SYS_PC4 0x0800
3bac3513	142
6d0f6bcf	143	#define CONFIG_SYS_DS1 CONFIG_SYS_PC4
3bac3513 WD	144
	145	/*
	146	* Very early board init code (fpga boot, etc.)
	147	*/
c837dcb1	148	int board_early_init_f (void)
3bac3513	149	{
6d0f6bcf	150	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
3bac3513	151
c83bf6a2 WD	152	/*
	153	* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
	154	*/
6d0f6bcf JCPV	155	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */
	156	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */
	157	immr->im_ioport.iop_pcdir \|= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */
3bac3513	158
c83bf6a2	159	return (0); /* success */
3bac3513 WD	160	}
	161
	162	/*
	163	* Check Board Identity:
	164	*
	165	* Test ELPT860 ID string
	166	*
	167	* Return 1 if no second DRAM bank, otherwise returns 0
	168	*/
	169
c83bf6a2	170	int checkboard (void)
3bac3513	171	{
77ddac94	172	char *s = getenv ("serial#");
3bac3513	173
c83bf6a2 WD	174	if (!s \|\| strncmp (s, "ELPT860", 7))
c83bf6a2 WD	175	printf ("### No HW ID - assuming ELPT860\n");
8bde7f77	176
c83bf6a2	177	return (0); /* success */
3bac3513 WD	178	}
	179
	180	/* ------------------------------------------------------------------------- */
	181
9973e3c6	182	phys_size_t initdram (int board_type)
3bac3513	183	{
6d0f6bcf	184	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	185	volatile memctl8xx_t *memctl = &immap->im_memctl;
	186	long int size8, size9;
	187	long int size_b0 = 0;
	188
	189	/*
	190	* This sequence initializes SDRAM chips on ELPT860 board
	191	*/
	192	upmconfig (UPMA, (uint *) init_sdram_table,
	193	sizeof (init_sdram_table) / sizeof (uint));
	194
	195	memctl->memc_mptpr = 0x0200;
	196	memctl->memc_mamr = 0x18002111;
	197
	198	memctl->memc_mar = 0x00000088;
	199	memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
	200
	201	upmconfig (UPMA, (uint *) sdram_table,
	202	sizeof (sdram_table) / sizeof (uint));
	203
	204	/*
	205	* Preliminary prescaler for refresh (depends on number of
	206	* banks): This value is selected for four cycles every 62.4 us
	207	* with two SDRAM banks or four cycles every 31.2 us with one
	208	* bank. It will be adjusted after memory sizing.
	209	*/
6d0f6bcf	210	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
c83bf6a2 WD	211
	212	/*
	213	* The following value is used as an address (i.e. opcode) for
	214	* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	215	* the port size is 32bit the SDRAM does NOT "see" the lower two
	216	* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	217	* MICRON SDRAMs:
	218	* -> 0 00 010 0 010
	219	* \| \| \| \| +- Burst Length = 4
	220	* \| \| \| +----- Burst Type = Sequential
	221	* \| \| +------- CAS Latency = 2
	222	* \| +----------- Operating Mode = Standard
	223	* +-------------- Write Burst Mode = Programmed Burst Length
	224	*/
	225	memctl->memc_mar = 0x00000088;
	226
	227	/*
	228	* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	229	* preliminary addresses - these have to be modified after the
	230	* SDRAM size has been determined.
	231	*/
6d0f6bcf JCPV	232	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
6d0f6bcf JCPV	233	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
c83bf6a2	234
6d0f6bcf	235	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
c83bf6a2 WD	236
	237	udelay (200);
	238
	239	/* perform SDRAM initializsation sequence */
	240
	241	memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
	242	udelay (1);
	243	memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
	244	udelay (1);
	245
	246	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	247
	248	udelay (1000);
	249
	250	/*
	251	* Check Bank 0 Memory Size for re-configuration
	252	*
	253	* try 8 column mode
	254	*/
6d0f6bcf	255	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
77ddac94	256	SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2	257
3bac3513	258	udelay (1000);
3bac3513	259
c83bf6a2 WD	260	/*
	261	* try 9 column mode
	262	*/
6d0f6bcf	263	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
77ddac94	264	SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2 WD	265
	266	if (size8 < size9) { /* leave configuration at 9 columns */
	267	size_b0 = size9;
	268	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
	269	} else { /* back to 8 columns */
	270
	271	size_b0 = size8;
6d0f6bcf	272	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
c83bf6a2 WD	273	udelay (500);
	274	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	275	}
	276
	277	udelay (1000);
	278
	279	/*
	280	* Adjust refresh rate depending on SDRAM type, both banks
	281	* For types > 128 MBit leave it at the current (fast) rate
	282	*/
	283	if (size_b0 < 0x02000000) {
	284	/* reduce to 15.6 us (62.4 us / quad) */
6d0f6bcf	285	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
c83bf6a2 WD	286	udelay (1000);
	287	}
	288
	289	/*
	290	* Final mapping: map bigger bank first
	291	*/
6d0f6bcf JCPV	292	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
6d0f6bcf JCPV	293	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
3bac3513	294
c83bf6a2 WD	295	{
c83bf6a2 WD	296	unsigned long reg;
8bde7f77	297
c83bf6a2 WD	298	/* adjust refresh rate depending on SDRAM type, one bank */
c83bf6a2 WD	299	reg = memctl->memc_mptpr;
6d0f6bcf	300	reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
c83bf6a2 WD	301	memctl->memc_mptpr = reg;
c83bf6a2 WD	302	}
3bac3513	303
c83bf6a2	304	udelay (10000);
8bde7f77	305
c83bf6a2	306	return (size_b0);
3bac3513 WD	307	}
	308
	309	/* ------------------------------------------------------------------------- */
	310
	311	/*
	312	* Check memory range for valid RAM. A simple memory test determines
	313	* the actually available RAM size between addresses `base' and
	314	* `base + maxsize'. Some (not all) hardware errors are detected:
	315	* - short between address lines
	316	* - short between data lines
	317	*/
	318
8bde7f77	319	static long int
c83bf6a2	320	dram_size (long int mamr_value, long int *base, long int maxsize)
3bac3513	321	{
6d0f6bcf	322	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2	323	volatile memctl8xx_t *memctl = &immap->im_memctl;
8bde7f77	324
c83bf6a2	325	memctl->memc_mamr = mamr_value;
3bac3513	326
c83bf6a2	327	return (get_ram_size (base, maxsize));
3bac3513 WD	328	}
	329
	330	/* ------------------------------------------------------------------------- */
	331
6d0f6bcf JCPV	332	#define CONFIG_SYS_PA1 0x4000
6d0f6bcf JCPV	333	#define CONFIG_SYS_PA2 0x2000
3bac3513	334
6d0f6bcf	335	#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 \| CONFIG_SYS_PA1)
3bac3513	336
c83bf6a2	337	void reset_phy (void)
3bac3513	338	{
6d0f6bcf	339	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	340
	341	/*
	342	* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
	343	* and no AUI loopback
	344	*/
6d0f6bcf JCPV	345	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */
	346	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */
	347	immr->im_ioport.iop_padir \|= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */
3bac3513	348	}