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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / LaCie / net2big_v2 / net2big_v2.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5628fb75
SG
2/*
3 * Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
4 *
5 * Based on Kirkwood support:
6 * (C) Copyright 2009
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5628fb75
SG
9 */
10
d678a59d 11#include <common.h>
5628fb75 12#include <command.h>
9fb625ce 13#include <env.h>
2af4d0f4 14#include <i2c.h>
691d719d 15#include <init.h>
5e6267af 16#include <net.h>
401d1c4f 17#include <asm/global_data.h>
c62db35d 18#include <asm/mach-types.h>
5628fb75 19#include <asm/arch/cpu.h>
3dc23f78 20#include <asm/arch/soc.h>
5628fb75
SG
21#include <asm/arch/mpp.h>
22#include <asm/arch/gpio.h>
77ea071f 23
5628fb75 24#include "net2big_v2.h"
77ea071f 25#include "../common/common.h"
7737c994 26#include "../common/cpld-gpio-bus.h"
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27
28DECLARE_GLOBAL_DATA_PTR;
29
30int board_early_init_f(void)
31{
32 /* GPIO configuration */
d5c5132f
SR
33 mvebu_config_gpio(NET2BIG_V2_OE_VAL_LOW, NET2BIG_V2_OE_VAL_HIGH,
34 NET2BIG_V2_OE_LOW, NET2BIG_V2_OE_HIGH);
5628fb75
SG
35
36 /* Multi-Purpose Pins Functionality configuration */
9d86f0c3 37 static const u32 kwmpp_config[] = {
5628fb75
SG
38 MPP0_SPI_SCn,
39 MPP1_SPI_MOSI,
40 MPP2_SPI_SCK,
41 MPP3_SPI_MISO,
42 MPP6_SYSRST_OUTn,
43 MPP7_GPO, /* Request power-off */
44 MPP8_TW_SDA,
45 MPP9_TW_SCK,
46 MPP10_UART0_TXD,
47 MPP11_UART0_RXD,
48 MPP13_GPIO, /* Rear power switch (on|auto) */
49 MPP14_GPIO, /* USB fuse alarm */
50 MPP15_GPIO, /* Rear power switch (auto|off) */
51 MPP16_GPIO, /* SATA HDD1 power */
52 MPP17_GPIO, /* SATA HDD2 power */
53 MPP20_SATA1_ACTn,
54 MPP21_SATA0_ACTn,
55 MPP24_GPIO, /* USB mode select */
56 MPP26_GPIO, /* USB device vbus */
57 MPP28_GPIO, /* USB enable host vbus */
7737c994 58 MPP29_GPIO, /* CPLD GPIO bus ALE */
5628fb75
SG
59 MPP34_GPIO, /* Rear Push button 0=on 1=off */
60 MPP35_GPIO, /* Inhibit switch power-off */
61 MPP36_GPIO, /* SATA HDD1 presence */
62 MPP37_GPIO, /* SATA HDD2 presence */
63 MPP40_GPIO, /* eSATA presence */
7737c994
SG
64 MPP44_GPIO, /* CPLD GPIO bus (data 0) */
65 MPP45_GPIO, /* CPLD GPIO bus (data 1) */
66 MPP46_GPIO, /* CPLD GPIO bus (data 2) */
67 MPP47_GPIO, /* CPLD GPIO bus (addr 0) */
68 MPP48_GPIO, /* CPLD GPIO bus (addr 1) */
69 MPP49_GPIO, /* CPLD GPIO bus (addr 2) */
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SG
70 0
71 };
72
84683638 73 kirkwood_mpp_conf(kwmpp_config, NULL);
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SG
74
75 return 0;
76}
77
78int board_init(void)
79{
80 /* Machine number */
81 gd->bd->bi_arch_number = MACH_TYPE_NET2BIG_V2;
82
83 /* Boot parameters address */
96c5f081 84 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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SG
85
86 return 0;
87}
88
77ea071f 89#if defined(CONFIG_MISC_INIT_R)
2af4d0f4 90
65cc0e2a 91#if defined(CONFIG_CMD_I2C) && defined(CFG_SYS_I2C_G762_ADDR)
2af4d0f4
SG
92/*
93 * Start I2C fan (GMT G762 controller)
94 */
95static void init_fan(void)
96{
97 u8 data;
98
99 i2c_set_bus_num(0);
100
101 /* Enable open-loop and PWM modes */
102 data = 0x20;
65cc0e2a 103 if (i2c_write(CFG_SYS_I2C_G762_ADDR,
2af4d0f4
SG
104 G762_REG_FAN_CMD1, 1, &data, 1) != 0)
105 goto err;
106 data = 0;
65cc0e2a 107 if (i2c_write(CFG_SYS_I2C_G762_ADDR,
2af4d0f4
SG
108 G762_REG_SET_CNT, 1, &data, 1) != 0)
109 goto err;
110 /*
111 * RPM to PWM (set_out register) fan speed conversion array:
112 * 0 0x00
113 * 1500 0x04
114 * 2800 0x08
115 * 3400 0x0C
116 * 3700 0x10
117 * 4400 0x20
118 * 4700 0x30
119 * 4800 0x50
120 * 5200 0x80
121 * 5400 0xC0
122 * 5500 0xFF
123 *
124 * Start fan at low speed (2800 RPM):
125 */
126 data = 0x08;
65cc0e2a 127 if (i2c_write(CFG_SYS_I2C_G762_ADDR,
2af4d0f4
SG
128 G762_REG_SET_OUT, 1, &data, 1) != 0)
129 goto err;
130
131 return;
132err:
133 printf("Error: failed to start I2C fan @%02x\n",
65cc0e2a 134 CFG_SYS_I2C_G762_ADDR);
2af4d0f4
SG
135}
136#else
137static void init_fan(void) {}
65cc0e2a 138#endif /* CONFIG_CMD_I2C && CFG_SYS_I2C_G762_ADDR */
2af4d0f4 139
7737c994
SG
140#if defined(CONFIG_NET2BIG_V2) && defined(CONFIG_KIRKWOOD_GPIO)
141/*
142 * CPLD GPIO bus:
143 *
144 * - address register : bit [0-2] -> GPIO [47-49]
145 * - data register : bit [0-2] -> GPIO [44-46]
146 * - enable register : GPIO 29
147 */
148static unsigned cpld_gpio_bus_addr[] = { 47, 48, 49 };
149static unsigned cpld_gpio_bus_data[] = { 44, 45, 46 };
150
151static struct cpld_gpio_bus cpld_gpio_bus = {
152 .addr = cpld_gpio_bus_addr,
153 .num_addr = ARRAY_SIZE(cpld_gpio_bus_addr),
154 .data = cpld_gpio_bus_data,
155 .num_data = ARRAY_SIZE(cpld_gpio_bus_data),
156 .enable = 29,
157};
158
159/*
160 * LEDs configuration:
161 *
162 * The LEDs are controlled by a CPLD and can be configured through
163 * the CPLD GPIO bus.
164 *
165 * Address register selection:
166 *
167 * addr | register
168 * ----------------------------
169 * 0 | front LED
170 * 1 | front LED brightness
171 * 2 | SATA LED brightness
172 * 3 | SATA0 LED
173 * 4 | SATA1 LED
174 * 5 | SATA2 LED
175 * 6 | SATA3 LED
176 * 7 | SATA4 LED
177 *
178 * Data register configuration:
179 *
180 * data | LED brightness
181 * -------------------------------------------------
182 * 0 | min (off)
183 * - | -
184 * 7 | max
185 *
186 * data | front LED mode
187 * -------------------------------------------------
188 * 0 | fix off
189 * 1 | fix blue on
190 * 2 | fix red on
191 * 3 | blink blue on=1 sec and blue off=1 sec
192 * 4 | blink red on=1 sec and red off=1 sec
193 * 5 | blink blue on=2.5 sec and red on=0.5 sec
194 * 6 | blink blue on=1 sec and red on=1 sec
195 * 7 | blink blue on=0.5 sec and blue off=2.5 sec
196 *
197 * data | SATA LED mode
198 * -------------------------------------------------
199 * 0 | fix off
200 * 1 | SATA activity blink
201 * 2 | fix red on
202 * 3 | blink blue on=1 sec and blue off=1 sec
203 * 4 | blink red on=1 sec and red off=1 sec
204 * 5 | blink blue on=2.5 sec and red on=0.5 sec
205 * 6 | blink blue on=1 sec and red on=1 sec
206 * 7 | fix blue on
207 */
208static void init_leds(void)
209{
210 /* Enable the front blue LED */
211 cpld_gpio_bus_write(&cpld_gpio_bus, 0, 1);
212 cpld_gpio_bus_write(&cpld_gpio_bus, 1, 3);
213
214 /* Configure SATA LEDs to blink in relation with the SATA activity */
215 cpld_gpio_bus_write(&cpld_gpio_bus, 3, 1);
216 cpld_gpio_bus_write(&cpld_gpio_bus, 4, 1);
217 cpld_gpio_bus_write(&cpld_gpio_bus, 2, 3);
218}
219#else
220static void init_leds(void) {}
221#endif /* CONFIG_NET2BIG_V2 && CONFIG_KIRKWOOD_GPIO */
222
5628fb75
SG
223int misc_init_r(void)
224{
2af4d0f4 225 init_fan();
77ea071f 226#if defined(CONFIG_CMD_I2C) && defined(CONFIG_SYS_I2C_EEPROM_ADDR)
00caae6d 227 if (!env_get("ethaddr")) {
5628fb75 228 uchar mac[6];
77ea071f 229 if (lacie_read_mac_address(mac) == 0)
fd1e959e 230 eth_env_set_enetaddr("ethaddr", mac);
5628fb75 231 }
77ea071f 232#endif
7737c994
SG
233 init_leds();
234
5628fb75
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235 return 0;
236}
2af4d0f4 237#endif /* CONFIG_MISC_INIT_R */
5628fb75 238
77ea071f 239#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
5628fb75
SG
240/* Configure and initialize PHY */
241void reset_phy(void)
242{
21b1c75f 243 mv_phy_88e1116_init("ethernet-controller@72000", 8);
5628fb75 244}
77ea071f 245#endif
5628fb75 246
77ea071f 247#if defined(CONFIG_KIRKWOOD_GPIO)
5628fb75
SG
248/* Return GPIO push button status */
249static int
09140113
SG
250do_read_push_button(struct cmd_tbl *cmdtp, int flag, int argc,
251 char *const argv[])
5628fb75
SG
252{
253 return !kw_gpio_get_value(NET2BIG_V2_GPIO_PUSH_BUTTON);
254}
255
256U_BOOT_CMD(button, 1, 1, do_read_push_button,
257 "Return GPIO push button status 0=off 1=on", "");
77ea071f 258#endif