]>
Commit | Line | Data |
---|---|---|
c7de829c WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca | |
4 | * | |
5 | * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker. | |
6 | * | |
7 | * Outline of the program based on eepro100.c which is | |
8 | * | |
9 | * (C) Copyright 2002 | |
10 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <common.h> | |
29 | #include <malloc.h> | |
30 | #include <net.h> | |
31 | #include <asm/io.h> | |
32 | #include <pci.h> | |
33 | ||
34 | #include "articiaS.h" | |
35 | #include "memio.h" | |
36 | ||
37 | /* 3Com Ethernet PCI definitions*/ | |
38 | ||
8bde7f77 | 39 | /* #define PCI_VENDOR_ID_3COM 0x10B7 */ |
c7de829c WD |
40 | #define PCI_DEVICE_ID_3COM_3C905C 0x9200 |
41 | ||
42 | /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */ | |
43 | ||
dd520bf3 WD |
44 | #define TotalReset (0<<11) |
45 | #define SelectWindow (1<<11) | |
46 | #define StartCoax (2<<11) | |
47 | #define RxDisable (3<<11) | |
48 | #define RxEnable (4<<11) | |
49 | #define RxReset (5<<11) | |
50 | #define UpStall (6<<11) | |
51 | #define UpUnstall (6<<11)+1 | |
52 | #define DownStall (6<<11)+2 | |
53 | #define DownUnstall (6<<11)+3 | |
54 | #define RxDiscard (8<<11) | |
55 | #define TxEnable (9<<11) | |
56 | #define TxDisable (10<<11) | |
57 | #define TxReset (11<<11) | |
58 | #define FakeIntr (12<<11) | |
59 | #define AckIntr (13<<11) | |
60 | #define SetIntrEnb (14<<11) | |
61 | #define SetStatusEnb (15<<11) | |
62 | #define SetRxFilter (16<<11) | |
63 | #define SetRxThreshold (17<<11) | |
64 | #define SetTxThreshold (18<<11) | |
65 | #define SetTxStart (19<<11) | |
66 | #define StartDMAUp (20<<11) | |
67 | #define StartDMADown (20<<11)+1 | |
c7de829c | 68 | #define StatsEnable (21<<11) |
8bde7f77 | 69 | #define StatsDisable (22<<11) |
dd520bf3 WD |
70 | #define StopCoax (23<<11) |
71 | #define SetFilterBit (25<<11) | |
c7de829c WD |
72 | |
73 | /* The SetRxFilter command accepts the following classes */ | |
74 | ||
dd520bf3 | 75 | #define RxStation 1 |
8bde7f77 WD |
76 | #define RxMulticast 2 |
77 | #define RxBroadcast 4 | |
dd520bf3 | 78 | #define RxProm 8 |
c7de829c WD |
79 | |
80 | /* 3Com status word defnitions */ | |
81 | ||
dd520bf3 WD |
82 | #define IntLatch 0x0001 |
83 | #define HostError 0x0002 | |
84 | #define TxComplete 0x0004 | |
85 | #define TxAvailable 0x0008 | |
86 | #define RxComplete 0x0010 | |
87 | #define RxEarly 0x0020 | |
88 | #define IntReq 0x0040 | |
89 | #define StatsFull 0x0080 | |
90 | #define DMADone (1<<8) | |
91 | #define DownComplete (1<<9) | |
92 | #define UpComplete (1<<10) | |
53677ef1 WD |
93 | #define DMAInProgress (1<<11) /* DMA controller is still busy.*/ |
94 | #define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/ | |
c7de829c WD |
95 | |
96 | /* Polling Registers */ | |
97 | ||
98 | #define DnPoll 0x2d | |
99 | #define UpPoll 0x3d | |
100 | ||
101 | /* Register window 0 offets */ | |
102 | ||
53677ef1 WD |
103 | #define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */ |
104 | #define Wn0EepromData 12 /* Window 0: EEPROM results register. */ | |
105 | #define IntrStatus 0x0E /* Valid in all windows. */ | |
c7de829c WD |
106 | |
107 | /* Register window 0 EEPROM bits */ | |
108 | ||
dd520bf3 WD |
109 | #define EEPROM_Read 0x80 |
110 | #define EEPROM_WRITE 0x40 | |
111 | #define EEPROM_ERASE 0xC0 | |
53677ef1 WD |
112 | #define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */ |
113 | #define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */ | |
c7de829c WD |
114 | |
115 | /* EEPROM locations. */ | |
116 | ||
8bde7f77 | 117 | #define PhysAddr01 0 |
c7de829c | 118 | #define PhysAddr23 1 |
8bde7f77 | 119 | #define PhysAddr45 2 |
c7de829c | 120 | #define ModelID 3 |
8bde7f77 WD |
121 | #define EtherLink3ID 7 |
122 | #define IFXcvrIO 8 | |
c7de829c | 123 | #define IRQLine 9 |
8bde7f77 WD |
124 | #define NodeAddr01 10 |
125 | #define NodeAddr23 11 | |
c7de829c | 126 | #define NodeAddr45 12 |
8bde7f77 | 127 | #define DriverTune 13 |
c7de829c WD |
128 | #define Checksum 15 |
129 | ||
130 | /* Register window 1 offsets, the window used in normal operation */ | |
131 | ||
dd520bf3 WD |
132 | #define TX_FIFO 0x10 |
133 | #define RX_FIFOa 0x10 | |
134 | #define RxErrors 0x14 | |
135 | #define RxStatus 0x18 | |
8bde7f77 | 136 | #define Timer 0x1A |
dd520bf3 | 137 | #define TxStatus 0x1B |
53677ef1 | 138 | #define TxFree 0x1C /* Remaining free bytes in Tx buffer. */ |
c7de829c WD |
139 | |
140 | /* Register Window 2 */ | |
8bde7f77 | 141 | |
c7de829c WD |
142 | #define Wn2_ResetOptions 12 |
143 | ||
144 | /* Register Window 3: MAC/config bits */ | |
145 | ||
53677ef1 | 146 | #define Wn3_Config 0 /* Internal Configuration */ |
c7de829c WD |
147 | #define Wn3_MAC_Ctrl 6 |
148 | #define Wn3_Options 8 | |
149 | ||
dd520bf3 | 150 | #define BFEXT(value, offset, bitcount) \ |
8bde7f77 | 151 | ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) |
c7de829c | 152 | |
53677ef1 | 153 | #define BFINS(lhs, rhs, offset, bitcount) \ |
dd520bf3 | 154 | (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ |
8bde7f77 | 155 | (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) |
c7de829c | 156 | |
53677ef1 | 157 | #define RAM_SIZE(v) BFEXT(v, 0, 3) |
dd520bf3 | 158 | #define RAM_WIDTH(v) BFEXT(v, 3, 1) |
53677ef1 WD |
159 | #define RAM_SPEED(v) BFEXT(v, 4, 2) |
160 | #define ROM_SIZE(v) BFEXT(v, 6, 2) | |
dd520bf3 | 161 | #define RAM_SPLIT(v) BFEXT(v, 16, 2) |
53677ef1 | 162 | #define XCVR(v) BFEXT(v, 20, 4) |
dd520bf3 | 163 | #define AUTOSELECT(v) BFEXT(v, 24, 1) |
c7de829c WD |
164 | |
165 | /* Register Window 4: Xcvr/media bits */ | |
8bde7f77 | 166 | |
dd520bf3 WD |
167 | #define Wn4_FIFODiag 4 |
168 | #define Wn4_NetDiag 6 | |
c7de829c | 169 | #define Wn4_PhysicalMgmt 8 |
dd520bf3 | 170 | #define Wn4_Media 10 |
c7de829c | 171 | |
dd520bf3 WD |
172 | #define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */ |
173 | #define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */ | |
174 | #define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */ | |
175 | #define Media_LnkBeat 0x0800 | |
c7de829c WD |
176 | |
177 | /* Register Window 7: Bus Master control */ | |
178 | ||
dd520bf3 WD |
179 | #define Wn7_MasterAddr 0 |
180 | #define Wn7_MasterLen 6 | |
181 | #define Wn7_MasterStatus 12 | |
c7de829c WD |
182 | |
183 | /* Boomerang bus master control registers. */ | |
184 | ||
dd520bf3 | 185 | #define PktStatus 0x20 |
c7de829c | 186 | #define DownListPtr 0x24 |
dd520bf3 WD |
187 | #define FragAddr 0x28 |
188 | #define FragLen 0x2c | |
53677ef1 | 189 | #define TxFreeThreshold 0x2f |
dd520bf3 | 190 | #define UpPktStatus 0x30 |
53677ef1 | 191 | #define UpListPtr 0x38 |
c7de829c WD |
192 | |
193 | /* The Rx and Tx descriptor lists. */ | |
194 | ||
53677ef1 WD |
195 | #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ |
196 | #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ | |
c7de829c WD |
197 | |
198 | struct rx_desc_3com { | |
53677ef1 WD |
199 | u32 next; /* Last entry points to 0 */ |
200 | u32 status; /* FSH -> Frame Start Header */ | |
201 | u32 addr; /* Up to 63 addr/len pairs possible */ | |
202 | u32 length; /* Set LAST_FRAG to indicate last pair */ | |
c7de829c WD |
203 | }; |
204 | ||
205 | /* Values for the Rx status entry. */ | |
206 | ||
207 | #define RxDComplete 0x00008000 | |
208 | #define RxDError 0x4000 | |
8bde7f77 WD |
209 | #define IPChksumErr (1<<25) |
210 | #define TCPChksumErr (1<<26) | |
c7de829c | 211 | #define UDPChksumErr (1<<27) |
8bde7f77 | 212 | #define IPChksumValid (1<<29) |
c7de829c WD |
213 | #define TCPChksumValid (1<<30) |
214 | #define UDPChksumValid (1<<31) | |
215 | ||
216 | struct tx_desc_3com { | |
53677ef1 WD |
217 | u32 next; /* Last entry points to 0 */ |
218 | u32 status; /* bits 0:12 length, others see below */ | |
8bde7f77 WD |
219 | u32 addr; |
220 | u32 length; | |
c7de829c WD |
221 | }; |
222 | ||
223 | /* Values for the Tx status entry. */ | |
224 | ||
225 | #define CRCDisable 0x2000 | |
226 | #define TxDComplete 0x8000 | |
227 | #define AddIPChksum 0x02000000 | |
228 | #define AddTCPChksum 0x04000000 | |
229 | #define AddUDPChksum 0x08000000 | |
53677ef1 | 230 | #define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */ |
c7de829c WD |
231 | |
232 | /* XCVR Types */ | |
233 | ||
234 | #define XCVR_10baseT 0 | |
8bde7f77 | 235 | #define XCVR_AUI 1 |
c7de829c | 236 | #define XCVR_10baseTOnly 2 |
8bde7f77 | 237 | #define XCVR_10base2 3 |
c7de829c WD |
238 | #define XCVR_100baseTx 4 |
239 | #define XCVR_100baseFx 5 | |
240 | #define XCVR_MII 6 | |
241 | #define XCVR_NWAY 8 | |
242 | #define XCVR_ExtMII 9 | |
53677ef1 | 243 | #define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */ |
c7de829c | 244 | |
53677ef1 WD |
245 | struct descriptor { /* A generic descriptor. */ |
246 | u32 next; /* Last entry points to 0 */ | |
247 | u32 status; /* FSH -> Frame Start Header */ | |
248 | u32 addr; /* Up to 63 addr/len pairs possible */ | |
249 | u32 length; /* Set LAST_FRAG to indicate last pair */ | |
c7de829c WD |
250 | }; |
251 | ||
252 | /* Misc. definitions */ | |
253 | ||
53677ef1 WD |
254 | #define NUM_RX_DESC PKTBUFSRX * 10 |
255 | #define NUM_TX_DESC 1 /* Number of TX descriptors */ | |
c7de829c WD |
256 | |
257 | #define TOUT_LOOP 1000000 | |
258 | ||
259 | #define ETH_ALEN 6 | |
260 | ||
261 | #define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD) | |
262 | #define EL3_CMD 0x0e | |
263 | #define EL3_STATUS 0x0e | |
264 | ||
265 | ||
266 | #undef ETH_DEBUG | |
267 | ||
268 | #ifdef ETH_DEBUG | |
53677ef1 | 269 | #define PRINTF(fmt,args...) printf (fmt ,##args) |
c7de829c WD |
270 | #else |
271 | #define PRINTF(fmt,args...) | |
272 | #endif | |
273 | ||
274 | ||
53677ef1 WD |
275 | static struct rx_desc_3com *rx_ring; /* RX descriptor ring */ |
276 | static struct tx_desc_3com *tx_ring; /* TX descriptor ring */ | |
277 | static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */ | |
278 | static int rx_next = 0; /* RX descriptor ring pointer */ | |
279 | static int tx_next = 0; /* TX descriptor ring pointer */ | |
c7de829c WD |
280 | static int tx_threshold; |
281 | ||
282 | static void init_rx_ring(struct eth_device* dev); | |
283 | static void purge_tx_ring(struct eth_device* dev); | |
284 | ||
285 | static void read_hw_addr(struct eth_device* dev, bd_t * bis); | |
286 | ||
287 | static int eth_3com_init(struct eth_device* dev, bd_t *bis); | |
288 | static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length); | |
289 | static int eth_3com_recv(struct eth_device* dev); | |
290 | static void eth_3com_halt(struct eth_device* dev); | |
291 | ||
292 | #define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a) | |
293 | #define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a) | |
294 | #define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) | |
295 | #define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) | |
296 | ||
297 | static inline int ETH_INL(struct eth_device* dev, u_long addr) | |
298 | { | |
299 | __asm volatile ("eieio"); | |
300 | return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase)); | |
301 | } | |
302 | ||
303 | static inline int ETH_INW(struct eth_device* dev, u_long addr) | |
304 | { | |
305 | __asm volatile ("eieio"); | |
306 | return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase)); | |
307 | } | |
308 | ||
309 | static inline int ETH_INB(struct eth_device* dev, u_long addr) | |
310 | { | |
311 | __asm volatile ("eieio"); | |
312 | return *(volatile u8 *)io_to_phys(addr + dev->iobase); | |
313 | } | |
314 | ||
315 | static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr) | |
316 | { | |
317 | *(volatile u8 *)io_to_phys(addr + dev->iobase) = command; | |
318 | __asm volatile ("eieio"); | |
319 | } | |
320 | ||
321 | static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr) | |
322 | { | |
323 | *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command); | |
324 | __asm volatile ("eieio"); | |
325 | } | |
326 | ||
327 | static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr) | |
328 | { | |
329 | *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command); | |
330 | __asm volatile ("eieio"); | |
331 | } | |
332 | ||
333 | static inline int ETH_STATUS(struct eth_device* dev) | |
334 | { | |
335 | __asm volatile ("eieio"); | |
336 | return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase)); | |
337 | } | |
338 | ||
339 | static inline void ETH_CMD(struct eth_device* dev, int command) | |
340 | { | |
8bde7f77 | 341 | *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command); |
c7de829c WD |
342 | __asm volatile ("eieio"); |
343 | } | |
344 | ||
345 | /* Command register is always in the same spot in all the register windows */ | |
346 | /* This function issues a command and waits for it so complete by checking the CmdInProgress bit */ | |
347 | ||
348 | static int issue_and_wait(struct eth_device* dev, int command) | |
349 | { | |
350 | ||
8bde7f77 | 351 | int i, status; |
c7de829c WD |
352 | |
353 | ETH_CMD(dev, command); | |
8bde7f77 WD |
354 | for (i = 0; i < 2000; i++) { |
355 | status = ETH_STATUS(dev); | |
356 | /*printf ("Issue: status 0x%4x.\n", status); */ | |
c7de829c | 357 | if (!(status & CmdInProgress)) |
8bde7f77 WD |
358 | return 1; |
359 | } | |
360 | ||
361 | /* OK, that didn't work. Do it the slow way. One second */ | |
362 | for (i = 0; i < 100000; i++) { | |
363 | status = ETH_STATUS(dev); | |
364 | /*printf ("Issue: status 0x%4x.\n", status); */ | |
365 | return 1; | |
366 | udelay(10); | |
367 | } | |
368 | PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) ); | |
c7de829c WD |
369 | return 0; |
370 | } | |
371 | ||
53677ef1 | 372 | /* Determine network media type and set up 3com accordingly */ |
c7de829c WD |
373 | /* I think I'm going to start with something known first like 10baseT */ |
374 | ||
53677ef1 | 375 | static int auto_negotiate (struct eth_device *dev) |
c7de829c | 376 | { |
53677ef1 | 377 | int i; |
c7de829c | 378 | |
53677ef1 | 379 | EL3WINDOW (dev, 1); |
c7de829c | 380 | |
53677ef1 WD |
381 | /* Wait for Auto negotiation to complete */ |
382 | for (i = 0; i <= 1000; i++) { | |
383 | if (ETH_INW (dev, 2) & 0x04) | |
384 | break; | |
385 | udelay (100); | |
c7de829c | 386 | |
53677ef1 WD |
387 | if (i == 1000) { |
388 | PRINTF ("Error: Auto negotiation failed\n"); | |
389 | return 0; | |
390 | } | |
c7de829c | 391 | } |
c7de829c WD |
392 | |
393 | ||
53677ef1 | 394 | return 1; |
c7de829c WD |
395 | } |
396 | ||
53677ef1 | 397 | void eth_interrupt (struct eth_device *dev) |
c7de829c | 398 | { |
53677ef1 | 399 | u16 status = ETH_STATUS (dev); |
c7de829c | 400 | |
53677ef1 | 401 | printf ("eth0: status = 0x%04x\n", status); |
c7de829c | 402 | |
53677ef1 WD |
403 | if (!(status & IntLatch)) |
404 | return; | |
405 | ||
406 | if (status & (1 << 6)) { | |
407 | ETH_CMD (dev, AckIntr | (1 << 6)); | |
408 | printf ("Acknowledged Interrupt command\n"); | |
409 | } | |
410 | ||
411 | if (status & DownComplete) { | |
412 | ETH_CMD (dev, AckIntr | DownComplete); | |
413 | printf ("Acknowledged DownComplete\n"); | |
414 | } | |
415 | ||
416 | if (status & UpComplete) { | |
417 | ETH_CMD (dev, AckIntr | UpComplete); | |
418 | printf ("Acknowledged UpComplete\n"); | |
419 | } | |
c7de829c | 420 | |
53677ef1 WD |
421 | ETH_CMD (dev, AckIntr | IntLatch); |
422 | printf ("Acknowledged IntLatch\n"); | |
c7de829c WD |
423 | } |
424 | ||
53677ef1 | 425 | int eth_3com_initialize (bd_t * bis) |
c7de829c | 426 | { |
8bde7f77 WD |
427 | u32 eth_iobase = 0, status; |
428 | int card_number = 0, ret; | |
53677ef1 | 429 | struct eth_device *dev; |
8bde7f77 | 430 | pci_dev_t devno; |
c7de829c WD |
431 | char *s; |
432 | ||
53677ef1 | 433 | s = getenv ("3com_base"); |
c7de829c WD |
434 | |
435 | /* Find ethernet controller on the PCI bus */ | |
436 | ||
53677ef1 WD |
437 | if ((devno = |
438 | pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, | |
439 | 0)) < 0) { | |
440 | PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n"); | |
c7de829c WD |
441 | goto Done; |
442 | } | |
443 | ||
53677ef1 WD |
444 | if (s) { |
445 | unsigned long base = atoi (s); | |
446 | ||
447 | pci_write_config_dword (devno, PCI_BASE_ADDRESS_0, | |
448 | base | 0x01); | |
c7de829c WD |
449 | } |
450 | ||
53677ef1 | 451 | ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, ð_iobase); |
8bde7f77 | 452 | eth_iobase &= ~0xf; |
c7de829c | 453 | |
53677ef1 | 454 | PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase); |
8bde7f77 | 455 | |
53677ef1 WD |
456 | pci_write_config_dword (devno, PCI_COMMAND, |
457 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
458 | PCI_COMMAND_MASTER); | |
c7de829c | 459 | |
53677ef1 | 460 | /* Check if I/O accesses and Bus Mastering are enabled */ |
c7de829c | 461 | |
53677ef1 | 462 | ret = pci_read_config_dword (devno, PCI_COMMAND, &status); |
c7de829c | 463 | |
53677ef1 WD |
464 | if (!(status & PCI_COMMAND_IO)) { |
465 | printf ("Error: Cannot enable IO access.\n"); | |
c7de829c WD |
466 | goto Done; |
467 | } | |
468 | ||
53677ef1 WD |
469 | if (!(status & PCI_COMMAND_MEMORY)) { |
470 | printf ("Error: Cannot enable MEMORY access.\n"); | |
c7de829c WD |
471 | goto Done; |
472 | } | |
473 | ||
53677ef1 WD |
474 | if (!(status & PCI_COMMAND_MASTER)) { |
475 | printf ("Error: Cannot enable Bus Mastering.\n"); | |
c7de829c WD |
476 | goto Done; |
477 | } | |
478 | ||
53677ef1 | 479 | dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */ |
c7de829c | 480 | |
53677ef1 | 481 | sprintf (dev->name, "3Com 3c920c#%d", card_number); |
8bde7f77 | 482 | dev->iobase = eth_iobase; |
53677ef1 WD |
483 | dev->priv = (void *) devno; |
484 | dev->init = eth_3com_init; | |
485 | dev->halt = eth_3com_halt; | |
486 | dev->send = eth_3com_send; | |
487 | dev->recv = eth_3com_recv; | |
c7de829c | 488 | |
53677ef1 | 489 | eth_register (dev); |
c7de829c | 490 | |
53677ef1 WD |
491 | /* { */ |
492 | /* char interrupt; */ | |
493 | /* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */ | |
494 | /* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */ | |
8bde7f77 | 495 | |
53677ef1 WD |
496 | /* printf("Installing eth0 interrupt handler to %d\n", interrupt); */ |
497 | /* irq_install_handler(interrupt, eth_interrupt, dev); */ | |
498 | /* } */ | |
c7de829c | 499 | |
8bde7f77 | 500 | card_number++; |
c7de829c WD |
501 | |
502 | /* Set the latency timer for value */ | |
53677ef1 WD |
503 | s = getenv ("3com_latency"); |
504 | if (s) { | |
505 | ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, | |
506 | (unsigned char) atoi (s)); | |
507 | } else | |
508 | ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a); | |
c7de829c | 509 | |
53677ef1 | 510 | read_hw_addr (dev, bis); /* get the MAC address from Window 2 */ |
c7de829c WD |
511 | |
512 | /* Reset the ethernet controller */ | |
513 | ||
514 | PRINTF ("Issuing reset command....\n"); | |
53677ef1 WD |
515 | if (!issue_and_wait (dev, TotalReset)) { |
516 | printf ("Error: Cannot reset ethernet controller.\n"); | |
c7de829c | 517 | goto Done; |
53677ef1 | 518 | } else |
c7de829c WD |
519 | PRINTF ("Ethernet controller reset.\n"); |
520 | ||
521 | /* allocate memory for rx and tx rings */ | |
522 | ||
53677ef1 | 523 | if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) { |
c7de829c WD |
524 | PRINTF ("Cannot allocate memory for RX_RING.....\n"); |
525 | goto Done; | |
526 | } | |
8bde7f77 | 527 | |
53677ef1 | 528 | if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) { |
c7de829c WD |
529 | PRINTF ("Cannot allocate memory for TX_RING.....\n"); |
530 | goto Done; | |
531 | } | |
8bde7f77 | 532 | |
c7de829c WD |
533 | Done: |
534 | return status; | |
535 | } | |
536 | ||
537 | ||
53677ef1 | 538 | static int eth_3com_init (struct eth_device *dev, bd_t * bis) |
c7de829c WD |
539 | { |
540 | int i, status = 0; | |
541 | int tx_cur, loop; | |
542 | u16 status_enable, intr_enable; | |
543 | struct descriptor *ias_cmd; | |
544 | ||
53677ef1 WD |
545 | /* Determine what type of network the machine is connected to */ |
546 | /* presently drops the connect to 10Mbps */ | |
c7de829c | 547 | |
53677ef1 WD |
548 | if (!auto_negotiate (dev)) { |
549 | printf ("Error: Cannot determine network media.\n"); | |
c7de829c WD |
550 | goto Done; |
551 | } | |
552 | ||
53677ef1 WD |
553 | issue_and_wait (dev, TxReset); |
554 | issue_and_wait (dev, RxReset | 0x04); | |
c7de829c | 555 | |
8bde7f77 | 556 | /* Switch to register set 7 for normal use. */ |
53677ef1 | 557 | EL3WINDOW (dev, 7); |
c7de829c WD |
558 | |
559 | /* Initialize Rx and Tx rings */ | |
560 | ||
53677ef1 WD |
561 | init_rx_ring (dev); |
562 | purge_tx_ring (dev); | |
c7de829c | 563 | |
53677ef1 | 564 | ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm); |
c7de829c | 565 | |
53677ef1 | 566 | issue_and_wait (dev, SetTxStart | 0x07ff); |
c7de829c | 567 | |
8bde7f77 | 568 | /* Below sets which indication bits to be seen. */ |
c7de829c | 569 | |
53677ef1 WD |
570 | status_enable = |
571 | SetStatusEnb | HostError | DownComplete | UpComplete | (1 << | |
572 | 6); | |
573 | ETH_CMD (dev, status_enable); | |
c7de829c WD |
574 | |
575 | /* Below sets no bits are to cause an interrupt since this is just polling */ | |
576 | ||
53677ef1 | 577 | intr_enable = SetIntrEnb; |
8bde7f77 | 578 | /* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */ |
53677ef1 WD |
579 | ETH_CMD (dev, intr_enable); |
580 | ETH_OUTB (dev, 127, UpPoll); | |
c7de829c | 581 | |
8bde7f77 | 582 | /* Ack all pending events, and set active indicator mask */ |
c7de829c | 583 | |
53677ef1 WD |
584 | ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq); |
585 | ETH_CMD (dev, intr_enable); | |
c7de829c WD |
586 | |
587 | /* Tell the adapter where the RX ring is located */ | |
588 | ||
53677ef1 WD |
589 | issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */ |
590 | ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr); | |
591 | ETH_CMD (dev, RxEnable); /* Enable the receiver. */ | |
592 | issue_and_wait (dev, UpUnstall); | |
c7de829c WD |
593 | |
594 | /* Send the Individual Address Setup frame */ | |
595 | ||
53677ef1 WD |
596 | tx_cur = tx_next; |
597 | tx_next = ((tx_next + 1) % NUM_TX_DESC); | |
c7de829c | 598 | |
53677ef1 WD |
599 | ias_cmd = (struct descriptor *) &tx_ring[tx_cur]; |
600 | ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */ | |
601 | ias_cmd->next = 0; | |
602 | ias_cmd->addr = cpu_to_le32 ((u32) & bis->bi_enetaddr[0]); | |
603 | ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG); | |
c7de829c WD |
604 | |
605 | /* Tell the adapter where the TX ring is located */ | |
606 | ||
53677ef1 WD |
607 | ETH_CMD (dev, TxEnable); /* Enable transmitter. */ |
608 | issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */ | |
609 | ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr); | |
610 | issue_and_wait (dev, DownUnstall); | |
611 | for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) { | |
612 | if (i >= TOUT_LOOP) { | |
613 | PRINTF ("TX Ring status (Init): 0x%4x\n", | |
614 | le32_to_cpu (tx_ring[tx_cur].status)); | |
615 | PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev)); | |
c7de829c WD |
616 | goto Done; |
617 | } | |
618 | } | |
53677ef1 WD |
619 | if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */ |
620 | ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */ | |
621 | issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */ | |
622 | ETH_OUTL (dev, 0, DownListPtr); | |
623 | issue_and_wait (dev, DownUnstall); | |
c7de829c WD |
624 | } |
625 | status = 1; | |
c7de829c WD |
626 | Done: |
627 | return status; | |
628 | } | |
629 | ||
53677ef1 | 630 | int eth_3com_send (struct eth_device *dev, volatile void *packet, int length) |
c7de829c WD |
631 | { |
632 | int i, status = 0; | |
633 | int tx_cur; | |
634 | ||
53677ef1 WD |
635 | if (length <= 0) { |
636 | PRINTF ("eth: bad packet size: %d\n", length); | |
c7de829c WD |
637 | goto Done; |
638 | } | |
639 | ||
53677ef1 WD |
640 | tx_cur = tx_next; |
641 | tx_next = (tx_next + 1) % NUM_TX_DESC; | |
c7de829c | 642 | |
53677ef1 WD |
643 | tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */ |
644 | tx_ring[tx_cur].next = 0; | |
645 | tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet)); | |
646 | tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG); | |
c7de829c WD |
647 | |
648 | /* Send the packet */ | |
649 | ||
53677ef1 WD |
650 | issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */ |
651 | ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr); | |
652 | issue_and_wait (dev, DownUnstall); | |
c7de829c | 653 | |
53677ef1 WD |
654 | for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) { |
655 | if (i >= TOUT_LOOP) { | |
656 | PRINTF ("TX Ring status (send): 0x%4x\n", | |
657 | le32_to_cpu (tx_ring[tx_cur].status)); | |
c7de829c WD |
658 | goto Done; |
659 | } | |
660 | } | |
53677ef1 WD |
661 | if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */ |
662 | ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */ | |
663 | issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */ | |
664 | ETH_OUTL (dev, 0, DownListPtr); | |
665 | issue_and_wait (dev, DownUnstall); | |
c7de829c | 666 | } |
53677ef1 WD |
667 | status = 1; |
668 | Done: | |
c7de829c WD |
669 | return status; |
670 | } | |
671 | ||
53677ef1 | 672 | void PrintPacket (uchar * packet, int length) |
c7de829c | 673 | { |
53677ef1 WD |
674 | int loop; |
675 | uchar *ptr; | |
c7de829c WD |
676 | |
677 | printf ("Printing packet of length %x.\n\n", length); | |
678 | ptr = packet; | |
53677ef1 | 679 | for (loop = 1; loop <= length; loop++) { |
c7de829c | 680 | printf ("%2x ", *ptr++); |
53677ef1 | 681 | if ((loop % 40) == 0) |
c7de829c WD |
682 | printf ("\n"); |
683 | } | |
684 | } | |
685 | ||
53677ef1 | 686 | int eth_3com_recv (struct eth_device *dev) |
c7de829c WD |
687 | { |
688 | u16 stat = 0; | |
689 | u32 status; | |
690 | int rx_prev, length = 0; | |
691 | ||
53677ef1 | 692 | while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */ |
c7de829c WD |
693 | ; |
694 | ||
53677ef1 | 695 | status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */ |
c7de829c | 696 | |
53677ef1 | 697 | while (status & (1 << 15)) { |
c7de829c WD |
698 | /* A packet has been received */ |
699 | ||
53677ef1 | 700 | if (status & (1 << 15)) { |
c7de829c | 701 | /* A valid frame received */ |
8bde7f77 | 702 | |
53677ef1 | 703 | length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */ |
8bde7f77 | 704 | |
c7de829c WD |
705 | /* Pass the packet up to the protocol layers */ |
706 | ||
53677ef1 WD |
707 | NetReceive ((uchar *) |
708 | le32_to_cpu (rx_ring[rx_next].addr), | |
709 | length); | |
710 | rx_ring[rx_next].status = 0; /* clear the status word */ | |
711 | ETH_CMD (dev, AckIntr | UpComplete); | |
712 | issue_and_wait (dev, UpUnstall); | |
713 | } else if (stat & HostError) { | |
c7de829c WD |
714 | /* There was an error */ |
715 | ||
53677ef1 WD |
716 | printf ("Rx error status: 0x%4x\n", stat); |
717 | init_rx_ring (dev); | |
c7de829c WD |
718 | goto Done; |
719 | } | |
720 | ||
721 | rx_prev = rx_next; | |
722 | rx_next = (rx_next + 1) % NUM_RX_DESC; | |
53677ef1 WD |
723 | stat = ETH_STATUS (dev); /* register status */ |
724 | status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */ | |
c7de829c | 725 | } |
c7de829c WD |
726 | Done: |
727 | return length; | |
728 | } | |
729 | ||
53677ef1 | 730 | void eth_3com_halt (struct eth_device *dev) |
c7de829c | 731 | { |
53677ef1 | 732 | if (!(dev->iobase)) { |
c7de829c WD |
733 | goto Done; |
734 | } | |
735 | ||
53677ef1 WD |
736 | issue_and_wait (dev, DownStall); /* shut down transmit and receive */ |
737 | issue_and_wait (dev, UpStall); | |
738 | issue_and_wait (dev, RxDisable); | |
739 | issue_and_wait (dev, TxDisable); | |
c7de829c | 740 | |
8bde7f77 WD |
741 | /* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */ |
742 | /* free(rx_ring); */ | |
c7de829c WD |
743 | |
744 | Done: | |
745 | return; | |
746 | } | |
747 | ||
53677ef1 | 748 | static void init_rx_ring (struct eth_device *dev) |
c7de829c WD |
749 | { |
750 | int i; | |
751 | ||
53677ef1 WD |
752 | PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer); |
753 | issue_and_wait (dev, UpStall); | |
c7de829c | 754 | |
53677ef1 WD |
755 | for (i = 0; i < NUM_RX_DESC; i++) { |
756 | rx_ring[i].next = | |
757 | cpu_to_le32 (((u32) & | |
758 | rx_ring[(i + 1) % NUM_RX_DESC])); | |
759 | rx_ring[i].status = 0; | |
760 | rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0])); | |
761 | rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG); | |
c7de829c WD |
762 | } |
763 | rx_next = 0; | |
764 | } | |
765 | ||
53677ef1 | 766 | static void purge_tx_ring (struct eth_device *dev) |
c7de829c WD |
767 | { |
768 | int i; | |
769 | ||
53677ef1 | 770 | PRINTF ("Purging tx_ring.\n"); |
c7de829c | 771 | |
53677ef1 | 772 | tx_next = 0; |
c7de829c | 773 | |
53677ef1 WD |
774 | for (i = 0; i < NUM_TX_DESC; i++) { |
775 | tx_ring[i].next = 0; | |
776 | tx_ring[i].status = 0; | |
777 | tx_ring[i].addr = 0; | |
778 | tx_ring[i].length = 0; | |
c7de829c WD |
779 | } |
780 | } | |
781 | ||
53677ef1 | 782 | static void read_hw_addr (struct eth_device *dev, bd_t * bis) |
c7de829c WD |
783 | { |
784 | u8 hw_addr[ETH_ALEN]; | |
785 | unsigned int eeprom[0x40]; | |
786 | unsigned int checksum = 0; | |
787 | int i, j, timer; | |
788 | ||
8bde7f77 | 789 | /* Read the station address from the EEPROM. */ |
c7de829c | 790 | |
53677ef1 WD |
791 | EL3WINDOW (dev, 0); |
792 | for (i = 0; i < 0x40; i++) { | |
793 | ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd); | |
8bde7f77 | 794 | /* Pause for at least 162 us. for the read to take place. */ |
53677ef1 WD |
795 | for (timer = 10; timer >= 0; timer--) { |
796 | udelay (162); | |
797 | if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0) | |
8bde7f77 WD |
798 | break; |
799 | } | |
53677ef1 | 800 | eeprom[i] = ETH_INW (dev, Wn0EepromData); |
8bde7f77 | 801 | } |
c7de829c WD |
802 | |
803 | /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */ | |
804 | ||
8bde7f77 | 805 | for (i = 0; i < 0x21; i++) |
53677ef1 | 806 | checksum ^= eeprom[i]; |
8bde7f77 | 807 | checksum = (checksum ^ (checksum >> 8)) & 0xff; |
c7de829c | 808 | |
8bde7f77 | 809 | if (checksum != 0xbb) |
53677ef1 WD |
810 | printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n", |
811 | checksum); | |
c7de829c | 812 | |
53677ef1 WD |
813 | for (i = 0, j = 0; i < 3; i++) { |
814 | hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff); | |
815 | hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff); | |
c7de829c WD |
816 | } |
817 | ||
818 | /* MAC Address is in window 2, write value from EEPROM to window 2 */ | |
819 | ||
53677ef1 | 820 | EL3WINDOW (dev, 2); |
8bde7f77 | 821 | for (i = 0; i < 6; i++) |
53677ef1 | 822 | ETH_OUTB (dev, hw_addr[i], i); |
c7de829c | 823 | |
53677ef1 WD |
824 | for (j = 0; j < ETH_ALEN; j += 2) { |
825 | hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff); | |
826 | hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff); | |
c7de829c WD |
827 | } |
828 | ||
53677ef1 WD |
829 | for (i = 0; i < ETH_ALEN; i++) { |
830 | if (hw_addr[i] != bis->bi_enetaddr[i]) { | |
831 | /* printf("Warning: HW address don't match:\n"); */ | |
832 | /* printf("Address in 3Com Window 2 is " */ | |
833 | /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ | |
834 | /* hw_addr[0], hw_addr[1], hw_addr[2], */ | |
835 | /* hw_addr[3], hw_addr[4], hw_addr[5]); */ | |
836 | /* printf("Address used by U-Boot is " */ | |
837 | /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */ | |
838 | /* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */ | |
839 | /* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */ | |
840 | /* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */ | |
841 | /* goto Done; */ | |
842 | char buffer[256]; | |
843 | ||
844 | if (bis->bi_enetaddr[0] == 0 | |
845 | && bis->bi_enetaddr[1] == 0 | |
846 | && bis->bi_enetaddr[2] == 0 | |
847 | && bis->bi_enetaddr[3] == 0 | |
848 | && bis->bi_enetaddr[4] == 0 | |
849 | && bis->bi_enetaddr[5] == 0) { | |
850 | ||
851 | sprintf (buffer, | |
852 | "%02X:%02X:%02X:%02X:%02X:%02X", | |
853 | hw_addr[0], hw_addr[1], hw_addr[2], | |
854 | hw_addr[3], hw_addr[4], hw_addr[5]); | |
855 | setenv ("ethaddr", buffer); | |
856 | } | |
c7de829c WD |
857 | } |
858 | } | |
859 | ||
53677ef1 WD |
860 | for (i = 0; i < ETH_ALEN; i++) |
861 | dev->enetaddr[i] = hw_addr[i]; | |
c7de829c WD |
862 | |
863 | Done: | |
864 | return; | |
865 | } |