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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aefb8f4c PS |
2 | /* |
3 | * | |
4 | * Copyright (C) 2015 Phil Sutter <phil@nwl.cc> | |
aefb8f4c PS |
5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
aefb8f4c | 9 | #include <miiphy.h> |
401d1c4f | 10 | #include <asm/global_data.h> |
aefb8f4c PS |
11 | #include <asm/io.h> |
12 | #include <asm/arch/cpu.h> | |
13 | #include <asm/arch/soc.h> | |
cd93d625 | 14 | #include <linux/bitops.h> |
aefb8f4c PS |
15 | #include <linux/mbus.h> |
16 | ||
17 | #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" | |
18 | #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" | |
19 | #include "../arch/arm/mach-mvebu/serdes/axp/board_env_spec.h" | |
20 | ||
a770159f PS |
21 | #include "cmd_syno.h" |
22 | ||
aefb8f4c PS |
23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
25 | /* GPP and MPP settings as found in mvBoardEnvSpec.c of Synology's U-Boot */ | |
26 | ||
27 | #define DS414_GPP_OUT_VAL_LOW (BIT(25) | BIT(30)) | |
28 | #define DS414_GPP_OUT_VAL_MID (BIT(10) | BIT(15)) | |
29 | #define DS414_GPP_OUT_VAL_HIGH (0) | |
30 | ||
31 | #define DS414_GPP_OUT_POL_LOW (0) | |
32 | #define DS414_GPP_OUT_POL_MID (0) | |
33 | #define DS414_GPP_OUT_POL_HIGH (0) | |
34 | ||
35 | #define DS414_GPP_OUT_ENA_LOW (~(BIT(25) | BIT(30))) | |
36 | #define DS414_GPP_OUT_ENA_MID (~(BIT(10) | BIT(12) | \ | |
37 | BIT(13) | BIT(14) | BIT(15))) | |
38 | #define DS414_GPP_OUT_ENA_HIGH (~0) | |
39 | ||
40 | static const u32 ds414_mpp_control[] = { | |
41 | 0x11111111, | |
42 | 0x22221111, | |
43 | 0x22222222, | |
44 | 0x00000000, | |
45 | 0x11110000, | |
46 | 0x00004000, | |
47 | 0x00000000, | |
48 | 0x00000000, | |
49 | 0x00000000 | |
50 | }; | |
51 | ||
52 | /* DDR3 static MC configuration */ | |
53 | ||
54 | /* 1G_v1 (4x2Gbits) adapted by DS414 */ | |
55 | MV_DRAM_MC_INIT syno_ddr3_b0_667_1g_v1[MV_MAX_DDR3_STATIC_SIZE] = { | |
56 | {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ | |
57 | {0x00001404, 0x30000800}, /*Dunit Control Low Register */ | |
58 | {0x00001408, 0x44148887}, /*DDR SDRAM Timing (Low) Register */ | |
59 | {0x0000140C, 0x3AD83FEA}, /*DDR SDRAM Timing (High) Register */ | |
60 | ||
61 | {0x00001410, 0x14000000}, /*DDR SDRAM Address Control Register */ | |
62 | ||
63 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
64 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
65 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
66 | {0x00001424, 0x0000F3FF}, /*Dunit Control High Register */ | |
67 | {0x00001428, 0x000F8830}, /*Dunit Control High Register */ | |
68 | {0x0000142C, 0x054C36F4}, /*Dunit Control High Register */ | |
69 | {0x0000147C, 0x0000C671}, | |
70 | ||
71 | {0x000014a0, 0x00000001}, | |
72 | {0x000014a8, 0x00000100}, /*2:1 */ | |
73 | {0x00020220, 0x00000006}, | |
74 | ||
75 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
76 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
77 | {0x0000149C, 0x00000001}, /*DDR Dunit ODT Control Register */ | |
78 | ||
79 | {0x000014C0, 0x192424C9}, /* DRAM address and Control Driving Strenght */ | |
80 | {0x000014C4, 0x0AAA24C9}, /* DRAM Data and DQS Driving Strenght */ | |
81 | ||
82 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence*/ | |
83 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
84 | ||
85 | {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ | |
86 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
87 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
88 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
89 | ||
90 | {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ | |
91 | {0x0000153C, 0x00000009}, /*Read Data Ready Delay Register */ | |
92 | ||
93 | {0x000015D0, 0x00000650}, /*MR0 */ | |
94 | {0x000015D4, 0x00000044}, /*MR1 */ | |
95 | {0x000015D8, 0x00000010}, /*MR2 */ | |
96 | {0x000015DC, 0x00000000}, /*MR3 */ | |
97 | ||
98 | {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ | |
99 | {0x000015EC, 0xF800A225}, /*DDR PHY */ | |
100 | ||
101 | {0x0, 0x0} | |
102 | }; | |
103 | ||
104 | MV_DRAM_MODES ds414_ddr_modes[MV_DDR3_MODES_NUMBER] = { | |
105 | {"ds414_1333-667", 0x3, 0x5, 0x0, A0, syno_ddr3_b0_667_1g_v1, NULL}, | |
106 | }; | |
107 | ||
108 | extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; | |
109 | ||
110 | MV_BIN_SERDES_CFG ds414_serdes_cfg[] = { | |
111 | { MV_PEX_ROOT_COMPLEX, 0x02011111, 0x00000000, | |
112 | { PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, | |
113 | PEX_BUS_DISABLED }, | |
114 | 0x0040, serdes_change_m_phy | |
115 | } | |
116 | }; | |
117 | ||
118 | MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) | |
119 | { | |
120 | return &ds414_ddr_modes[0]; | |
121 | } | |
122 | ||
0a590243 | 123 | MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) |
aefb8f4c PS |
124 | { |
125 | return &ds414_serdes_cfg[0]; | |
126 | } | |
127 | ||
128 | u8 board_sat_r_get(u8 dev_num, u8 reg) | |
129 | { | |
0a590243 | 130 | return 0xf; /* All PEX ports support PCIe Gen2 */ |
aefb8f4c PS |
131 | } |
132 | ||
133 | int board_early_init_f(void) | |
134 | { | |
135 | int i; | |
136 | ||
137 | /* Set GPP Out value */ | |
138 | reg_write(GPP_DATA_OUT_REG(0), DS414_GPP_OUT_VAL_LOW); | |
139 | reg_write(GPP_DATA_OUT_REG(1), DS414_GPP_OUT_VAL_MID); | |
140 | reg_write(GPP_DATA_OUT_REG(2), DS414_GPP_OUT_VAL_HIGH); | |
141 | ||
142 | /* set GPP polarity */ | |
143 | reg_write(GPP_DATA_IN_POL_REG(0), DS414_GPP_OUT_POL_LOW); | |
144 | reg_write(GPP_DATA_IN_POL_REG(1), DS414_GPP_OUT_POL_MID); | |
145 | reg_write(GPP_DATA_IN_POL_REG(2), DS414_GPP_OUT_POL_HIGH); | |
146 | ||
147 | /* Set GPP Out Enable */ | |
148 | reg_write(GPP_DATA_OUT_EN_REG(0), DS414_GPP_OUT_ENA_LOW); | |
149 | reg_write(GPP_DATA_OUT_EN_REG(1), DS414_GPP_OUT_ENA_MID); | |
150 | reg_write(GPP_DATA_OUT_EN_REG(2), DS414_GPP_OUT_ENA_HIGH); | |
151 | ||
152 | for (i = 0; i < ARRAY_SIZE(ds414_mpp_control); i++) | |
153 | reg_write(MPP_CONTROL_REG(i), ds414_mpp_control[i]); | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | int board_init(void) | |
159 | { | |
160 | u32 pwr_mng_ctrl_reg; | |
161 | ||
162 | /* Adress of boot parameters */ | |
163 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | |
164 | ||
165 | /* Gate unused clocks | |
166 | * | |
167 | * Note: Disabling unused PCIe lanes will hang PCI bus scan. | |
168 | * Once this is resolved, bits 10-12, 26 and 27 can be | |
169 | * unset here as well. | |
170 | */ | |
171 | pwr_mng_ctrl_reg = reg_read(POWER_MNG_CTRL_REG); | |
172 | pwr_mng_ctrl_reg &= ~(BIT(0)); /* Audio */ | |
173 | pwr_mng_ctrl_reg &= ~(BIT(1) | BIT(2)); /* GE3, GE2 */ | |
174 | pwr_mng_ctrl_reg &= ~(BIT(14) | BIT(15)); /* SATA0 link and core */ | |
175 | pwr_mng_ctrl_reg &= ~(BIT(16)); /* LCD */ | |
176 | pwr_mng_ctrl_reg &= ~(BIT(17)); /* SDIO */ | |
177 | pwr_mng_ctrl_reg &= ~(BIT(19) | BIT(20)); /* USB1 and USB2 */ | |
178 | pwr_mng_ctrl_reg &= ~(BIT(29) | BIT(30)); /* SATA1 link and core */ | |
179 | reg_write(POWER_MNG_CTRL_REG, pwr_mng_ctrl_reg); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
a770159f PS |
184 | int misc_init_r(void) |
185 | { | |
186 | if (!env_get("ethaddr")) { | |
187 | puts("Incomplete environment, populating from SPI flash\n"); | |
188 | do_syno_populate(0, NULL); | |
189 | } | |
190 | return 0; | |
191 | } | |
192 | ||
aefb8f4c PS |
193 | int checkboard(void) |
194 | { | |
195 | puts("Board: DS414\n"); | |
196 | ||
197 | return 0; | |
198 | } |