[people/ms/u-boot.git] / board / ads5121 / ads5121.c

/*
 * (C) Copyright 2007 DENX Software Engineering
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <mpc512x.h>
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>

/* Clocks in use */
#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
			 CLOCK_SCCR1_LPC_EN |				\
			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
			 CLOCK_SCCR1_PSCFIFO_EN |			\
			 CLOCK_SCCR1_DDR_EN |				\
			 CLOCK_SCCR1_FEC_EN)

#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
			 CLOCK_SCCR2_SPDIF_EN |		\
			 CLOCK_SCCR2_I2C_EN)

#define CSAW_START(start)	((start) & 0xFFFF0000)
#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)

long int fixed_sdram(void);

int board_early_init_f (void)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 lpcaw;

	/*
	 * Initialize Local Window for the CPLD registers access (CS2 selects
	 * the CPLD chip)
	 */
	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
			      CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
	im->lpc.cs_cfg[2] = CFG_CS2_CFG;

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lpcaw = im->sysconf.lpcs2aw;
	__asm__ __volatile__ ("isync");

	/*
	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
	 *
	 * Without this the flash identification routine fails, as it needs to issue
	 * write commands in order to establish the device ID.
	 */
	*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;

	/*
	 * Enable clocks
	 */
	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
	im->clk.sccr[1] = SCCR2_CLOCKS_EN;

	return 0;
}

long int initdram (int board_type)
{
	u32 msize = 0;

	msize = fixed_sdram ();

	return msize;
}

/*
 * fixed sdram init -- the board doesn't use memory modules that have serial presence
 * detect or similar mechanism for discovery of the DRAM settings
 */
long int fixed_sdram (void)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
	u32 msize_log2 = __ilog2 (msize);
	u32 i;

	/* Initialize IO Control */
	im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;

	/* Initialize DDR Local Window */
	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
	im->sysconf.ddrlaw.ar = msize_log2 - 1;

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	i = im->sysconf.ddrlaw.ar;
	__asm__ __volatile__ ("isync");

	/* Enable DDR */
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;

	/* Initialize DDR Priority Manager */
	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;

	/* Initialize MDDRC */
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;

	/* Initialize DDR */
	for (i = 0; i < 10; i++)
		im->mddrc.ddr_command = CFG_MICRON_NOP;

	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_EM2;
	im->mddrc.ddr_command = CFG_MICRON_EM3;
	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
	im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
	im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;

	for (i = 0; i < 10; i++)
		im->mddrc.ddr_command = CFG_MICRON_NOP;

	/* Start MDDRC */
	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;

	return msize;
}

int checkboard (void)
{
	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	volatile unsigned long *reg;
	int i;

	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
		brd_rev, cpld_rev);

	/* change the slew rate on all pata pins to max */
	reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
	for (i = 0; i < 9; i++)
		reg[i] |= 0x00000003;
	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8993e54b RJ	1	/*
	2	* (C) Copyright 2007 DENX Software Engineering
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc512x.h>
	26	#include <asm/bitops.h>
	27	#include <command.h>
e343ab83	28	#include <fdt_support.h>
8993e54b RJ	29
	30	/* Clocks in use */
	31	#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN \| \
	32	CLOCK_SCCR1_LPC_EN \| \
	33	CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) \| \
	34	CLOCK_SCCR1_PSCFIFO_EN \| \
	35	CLOCK_SCCR1_DDR_EN \| \
	36	CLOCK_SCCR1_FEC_EN)
	37
	38	#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN \| \
	39	CLOCK_SCCR2_SPDIF_EN \| \
	40	CLOCK_SCCR2_I2C_EN)
	41
	42	#define CSAW_START(start) ((start) & 0xFFFF0000)
	43	#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
	44
	45	long int fixed_sdram(void);
	46
	47	int board_early_init_f (void)
	48	{
	49	volatile immap_t im = (immap_t ) CFG_IMMR;
	50	u32 lpcaw;
	51
	52	/*
	53	* Initialize Local Window for the CPLD registers access (CS2 selects
	54	* the CPLD chip)
	55	*/
	56	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) \|
	57	CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
	58	im->lpc.cs_cfg[2] = CFG_CS2_CFG;
	59
	60	/*
	61	* According to MPC5121e RM, configuring local access windows should
	62	* be followed by a dummy read of the config register that was
	63	* modified last and an isync
	64	*/
	65	lpcaw = im->sysconf.lpcs2aw;
	66	__asm__ __volatile__ ("isync");
	67
	68	/*
	69	* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
	70	*
	71	* Without this the flash identification routine fails, as it needs to issue
	72	* write commands in order to establish the device ID.
	73	*/
	74	((volatile u8 )(CFG_CPLD_BASE + 0x08)) = 0xC1;
	75
	76	/*
	77	* Enable clocks
	78	*/
	79	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
	80	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
	81
	82	return 0;
	83	}
	84
	85	long int initdram (int board_type)
	86	{
	87	u32 msize = 0;
	88
8993e54b	89	msize = fixed_sdram ();
8993e54b RJ	90
	91	return msize;
	92	}
	93
	94	/*
	95	* fixed sdram init -- the board doesn't use memory modules that have serial presence
	96	* detect or similar mechanism for discovery of the DRAM settings
	97	*/
	98	long int fixed_sdram (void)
	99	{
	100	volatile immap_t im = (immap_t ) CFG_IMMR;
	101	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
	102	u32 msize_log2 = __ilog2 (msize);
	103	u32 i;
	104
	105	/* Initialize IO Control */
	106	im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
	107
	108	/* Initialize DDR Local Window */
	109	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
	110	im->sysconf.ddrlaw.ar = msize_log2 - 1;
	111
	112	/*
	113	* According to MPC5121e RM, configuring local access windows should
	114	* be followed by a dummy read of the config register that was
	115	* modified last and an isync
b1b54e35	116	*/
8993e54b RJ	117	i = im->sysconf.ddrlaw.ar;
	118	__asm__ __volatile__ ("isync");
	119
	120	/* Enable DDR */
	121	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
	122
	123	/* Initialize DDR Priority Manager */
	124	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
	125	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
	126	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
	127	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
	128	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
	129	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
	130	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
	131	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
	132	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
	133	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
	134	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
	135	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
	136	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
	137	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
	138	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
	139	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
	140	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
	141	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
	142	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
	143	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
	144	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
	145	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
	146	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
	147
	148	/* Initialize MDDRC */
	149	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
	150	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
	151	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
	152	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
	153
	154	/* Initialize DDR */
	155	for (i = 0; i < 10; i++)
	156	im->mddrc.ddr_command = CFG_MICRON_NOP;
	157
	158	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	159	im->mddrc.ddr_command = CFG_MICRON_EM2;
	160	im->mddrc.ddr_command = CFG_MICRON_EM3;
	161	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
	162	im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
	163	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	164	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	165	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	166	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
	167	im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
	168
	169	for (i = 0; i < 10; i++)
	170	im->mddrc.ddr_command = CFG_MICRON_NOP;
	171
	172	/* Start MDDRC */
	173	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
	174	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
	175
	176	return msize;
	177	}
	178
	179	int checkboard (void)
	180	{
181	ushort brd_rev = (vu_short ) (CFG_CPLD_BASE + 0x00);
182	uchar cpld_rev = (vu_char ) (CFG_CPLD_BASE + 0x02);
51b67d06 JR	183	volatile immap_t im = (immap_t ) CFG_IMMR;
	184	volatile unsigned long *reg;
	185	int i;
8993e54b RJ	186
8993e54b RJ	187	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
b1b54e35	188	brd_rev, cpld_rev);
51b67d06 JR	189
	190	/* change the slew rate on all pata pins to max */
	191	reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
	192	for (i = 0; i < 9; i++)
	193	reg[i] \|= 0x00000003;
8993e54b RJ	194	return 0;
8993e54b RJ	195	}
281ff9a4 GB	196
	197	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	198	void ft_board_setup(void blob, bd_t bd)
	199	{
	200	ft_cpu_setup(blob, bd);
	201	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
	202	}
	203	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */