[people/ms/u-boot.git] / board / ads5121 / ads5121.c

/*
 * (C) Copyright 2007 DENX Software Engineering
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <mpc512x.h>
#include "iopin.h"
#include <asm/bitops.h>
#include <command.h>
#include <fdt_support.h>
#ifdef CONFIG_MISC_INIT_R
#include <i2c.h>
#endif
#include "iopin.h"	/* for iopin_initialize() prototype */

/* Clocks in use */
#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
			 CLOCK_SCCR1_LPC_EN |				\
			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
			 CLOCK_SCCR1_PSCFIFO_EN |			\
			 CLOCK_SCCR1_DDR_EN |				\
			 CLOCK_SCCR1_FEC_EN |				\
			 CLOCK_SCCR1_PCI_EN |				\
			 CLOCK_SCCR1_TPR_EN)

#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
			 CLOCK_SCCR2_SPDIF_EN |		\
			 CLOCK_SCCR2_DIU_EN |		\
			 CLOCK_SCCR2_I2C_EN)

#define CSAW_START(start)	((start) & 0xFFFF0000)
#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)

extern void ads5121_diu_init(void);

long int fixed_sdram(void);

int board_early_init_f (void)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 lpcaw;

	/*
	 * Initialize Local Window for the CPLD registers access (CS2 selects
	 * the CPLD chip)
	 */
	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
			      CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
	im->lpc.cs_cfg[2] = CFG_CS2_CFG;

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	lpcaw = im->sysconf.lpcs2aw;
	__asm__ __volatile__ ("isync");

	/*
	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
	 *
	 * Without this the flash identification routine fails, as it needs to issue
	 * write commands in order to establish the device ID.
	 */

#ifdef CONFIG_ADS5121_REV2
	*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
#else
	if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
	} else {
		/* running from Backup flash */
		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
	}
#endif
	/*
	 * Configure Flash Speed
	 */
	*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
	/*
	 * Enable clocks
	 */
	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
	im->clk.sccr[1] = SCCR2_CLOCKS_EN;

	return 0;
}

phys_size_t initdram (int board_type)
{
	u32 msize = 0;

	msize = fixed_sdram ();

	return msize;
}

/*
 * fixed sdram init -- the board doesn't use memory modules that have serial presence
 * detect or similar mechanism for discovery of the DRAM settings
 */
long int fixed_sdram (void)
{
	volatile immap_t *im = (immap_t *) CFG_IMMR;
	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
	u32 msize_log2 = __ilog2 (msize);
	u32 i;

	/* Initialize IO Control */
	im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;

	/* Initialize DDR Local Window */
	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
	im->sysconf.ddrlaw.ar = msize_log2 - 1;

	/*
	 * According to MPC5121e RM, configuring local access windows should
	 * be followed by a dummy read of the config register that was
	 * modified last and an isync
	 */
	i = im->sysconf.ddrlaw.ar;
	__asm__ __volatile__ ("isync");

	/* Enable DDR */
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;

	/* Initialize DDR Priority Manager */
	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;

	/* Initialize MDDRC */
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;

	/* Initialize DDR */
	for (i = 0; i < 10; i++)
		im->mddrc.ddr_command = CFG_MICRON_NOP;

	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_NOP;
	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	im->mddrc.ddr_command = CFG_MICRON_NOP;
	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	im->mddrc.ddr_command = CFG_MICRON_NOP;
	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	im->mddrc.ddr_command = CFG_MICRON_NOP;
	im->mddrc.ddr_command = CFG_MICRON_EM2;
	im->mddrc.ddr_command = CFG_MICRON_NOP;
	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_EM2;
	im->mddrc.ddr_command = CFG_MICRON_EM3;
	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	im->mddrc.ddr_command = CFG_MICRON_NOP;

	/* Start MDDRC */
	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;

	return msize;
}

int misc_init_r(void)
{
	u8 tmp_val;
	extern int ads5121_diu_init(void);

	/* Using this for DIU init before the driver in linux takes over
	 *  Enable the TFP410 Encoder (I2C address 0x38)
	 */

	i2c_set_bus_num(2);
	tmp_val = 0xBF;
	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);

	tmp_val = 0x10;
	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	/* Verify if enabled */
	tmp_val = 0;
	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);

#ifdef CONFIG_FSL_DIU_FB
#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
	ads5121_diu_init();
#endif
#endif

	return 0;
}

int checkboard (void)
{
	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);

	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
		brd_rev, cpld_rev);
	/* initialize function mux & slew rate IO inter alia on IO Pins  */
	iopin_initialize();

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8993e54b RJ	1	/*
	2	* (C) Copyright 2007 DENX Software Engineering
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc512x.h>
b60b8573	26	#include "iopin.h"
8993e54b RJ	27	#include <asm/bitops.h>
8993e54b RJ	28	#include <command.h>
e343ab83	29	#include <fdt_support.h>
f31c49db MM	30	#ifdef CONFIG_MISC_INIT_R
	31	#include <i2c.h>
	32	#endif
9b55a253 WD	33	#include "iopin.h" /* for iopin_initialize() prototype */
9b55a253 WD	34
8993e54b RJ	35	/* Clocks in use */
	36	#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN \| \
	37	CLOCK_SCCR1_LPC_EN \| \
	38	CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) \| \
	39	CLOCK_SCCR1_PSCFIFO_EN \| \
	40	CLOCK_SCCR1_DDR_EN \| \
8d103071	41	CLOCK_SCCR1_FEC_EN \| \
5f91db7f	42	CLOCK_SCCR1_PCI_EN \| \
8d103071	43	CLOCK_SCCR1_TPR_EN)
8993e54b RJ	44
	45	#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN \| \
	46	CLOCK_SCCR2_SPDIF_EN \| \
0e1bad47	47	CLOCK_SCCR2_DIU_EN \| \
8993e54b RJ	48	CLOCK_SCCR2_I2C_EN)
	49
	50	#define CSAW_START(start) ((start) & 0xFFFF0000)
	51	#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
	52
b60b8573 JR	53	extern void ads5121_diu_init(void);
b60b8573 JR	54
8993e54b RJ	55	long int fixed_sdram(void);
	56
	57	int board_early_init_f (void)
	58	{
	59	volatile immap_t im = (immap_t ) CFG_IMMR;
9b55a253	60	u32 lpcaw;
8993e54b RJ	61
	62	/*
	63	* Initialize Local Window for the CPLD registers access (CS2 selects
	64	* the CPLD chip)
	65	*/
	66	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) \|
	67	CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
	68	im->lpc.cs_cfg[2] = CFG_CS2_CFG;
	69
	70	/*
	71	* According to MPC5121e RM, configuring local access windows should
	72	* be followed by a dummy read of the config register that was
	73	* modified last and an isync
	74	*/
	75	lpcaw = im->sysconf.lpcs2aw;
	76	__asm__ __volatile__ ("isync");
	77
	78	/*
	79	* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
	80	*
	81	* Without this the flash identification routine fails, as it needs to issue
	82	* write commands in order to establish the device ID.
	83	*/
8993e54b	84
f31c49db MM	85	#ifdef CONFIG_ADS5121_REV2
	86	((volatile u8 )(CFG_CPLD_BASE + 0x08)) = 0xC1;
	87	#else
	88	if (((u8 )(CFG_CPLD_BASE + 0x08)) & 0x04) {
	89	((volatile u8 )(CFG_CPLD_BASE + 0x08)) = 0xC1;
	90	} else {
	91	/* running from Backup flash */
	92	((volatile u8 )(CFG_CPLD_BASE + 0x08)) = 0x32;
	93	}
	94	#endif
	95	/*
	96	* Configure Flash Speed
	97	*/
	98	((volatile u32 )(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
8993e54b RJ	99	/*
	100	* Enable clocks
	101	*/
	102	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
	103	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
	104
	105	return 0;
	106	}
	107
9973e3c6	108	phys_size_t initdram (int board_type)
8993e54b RJ	109	{
	110	u32 msize = 0;
	111
8993e54b	112	msize = fixed_sdram ();
8993e54b RJ	113
	114	return msize;
	115	}
	116
	117	/*
	118	* fixed sdram init -- the board doesn't use memory modules that have serial presence
	119	* detect or similar mechanism for discovery of the DRAM settings
	120	*/
	121	long int fixed_sdram (void)
	122	{
	123	volatile immap_t im = (immap_t ) CFG_IMMR;
	124	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
	125	u32 msize_log2 = __ilog2 (msize);
	126	u32 i;
	127
	128	/* Initialize IO Control */
	129	im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
	130
	131	/* Initialize DDR Local Window */
	132	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
	133	im->sysconf.ddrlaw.ar = msize_log2 - 1;
	134
	135	/*
	136	* According to MPC5121e RM, configuring local access windows should
	137	* be followed by a dummy read of the config register that was
	138	* modified last and an isync
b1b54e35	139	*/
8993e54b RJ	140	i = im->sysconf.ddrlaw.ar;
	141	__asm__ __volatile__ ("isync");
	142
	143	/* Enable DDR */
	144	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
	145
	146	/* Initialize DDR Priority Manager */
	147	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
	148	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
	149	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
	150	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
8993e54b	151	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
37e3c62f	152	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
8993e54b	153	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
37e3c62f	154	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
8993e54b	155	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
37e3c62f	156	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
8993e54b	157	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
37e3c62f	158	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
8993e54b RJ	159	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
8993e54b RJ	160	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
8d103071	161	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
37e3c62f	162	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
8993e54b	163	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
37e3c62f	164	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
8993e54b	165	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
37e3c62f	166	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
8993e54b	167	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
37e3c62f	168	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
8993e54b RJ	169	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
	170
	171	/* Initialize MDDRC */
	172	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
	173	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
	174	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
	175	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
	176
	177	/* Initialize DDR */
	178	for (i = 0; i < 10; i++)
	179	im->mddrc.ddr_command = CFG_MICRON_NOP;
	180
37e3c62f GB	181	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	182	im->mddrc.ddr_command = CFG_MICRON_NOP;
	183	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	184	im->mddrc.ddr_command = CFG_MICRON_NOP;
	185	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	186	im->mddrc.ddr_command = CFG_MICRON_NOP;
	187	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	188	im->mddrc.ddr_command = CFG_MICRON_NOP;
	189	im->mddrc.ddr_command = CFG_MICRON_EM2;
	190	im->mddrc.ddr_command = CFG_MICRON_NOP;
8993e54b RJ	191	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	192	im->mddrc.ddr_command = CFG_MICRON_EM2;
	193	im->mddrc.ddr_command = CFG_MICRON_EM3;
	194	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
37e3c62f	195	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
8993e54b RJ	196	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
	197	im->mddrc.ddr_command = CFG_MICRON_RFSH;
	198	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
	199	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
37e3c62f GB	200	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
37e3c62f GB	201	im->mddrc.ddr_command = CFG_MICRON_NOP;
8993e54b RJ	202
	203	/* Start MDDRC */
	204	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
	205	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
	206
	207	return msize;
	208	}
	209
0e1bad47 YS	210	int misc_init_r(void)
	211	{
	212	u8 tmp_val;
9b55a253	213	extern int ads5121_diu_init(void);
0e1bad47 YS	214
	215	/* Using this for DIU init before the driver in linux takes over
	216	* Enable the TFP410 Encoder (I2C address 0x38)
	217	*/
	218
	219	i2c_set_bus_num(2);
	220	tmp_val = 0xBF;
	221	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	222	/* Verify if enabled */
	223	tmp_val = 0;
	224	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
	225	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
	226
	227	tmp_val = 0x10;
	228	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	229	/* Verify if enabled */
	230	tmp_val = 0;
	231	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
	232	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
	233
	234	#ifdef CONFIG_FSL_DIU_FB
	235	#if !(defined(CONFIG_VIDEO) \|\| defined(CONFIG_CFB_CONSOLE))
	236	ads5121_diu_init();
	237	#endif
	238	#endif
	239
	240	return 0;
	241	}
	242
8993e54b RJ	243	int checkboard (void)
	244	{
	245	ushort brd_rev = (vu_short ) (CFG_CPLD_BASE + 0x00);
	246	uchar cpld_rev = (vu_char ) (CFG_CPLD_BASE + 0x02);
	247
	248	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
b1b54e35	249	brd_rev, cpld_rev);
16bee7b0 MM	250	/* initialize function mux & slew rate IO inter alia on IO Pins */
16bee7b0 MM	251	iopin_initialize();
51b67d06	252
8993e54b RJ	253	return 0;
8993e54b RJ	254	}
281ff9a4 GB	255
	256	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	257	void ft_board_setup(void blob, bd_t bd)
	258	{
	259	ft_cpu_setup(blob, bd);
	260	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
	261	}
	262	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */