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87a62bce CP |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * (C) Copyright 2010, 2018 | |
4 | * Allied Telesis <www.alliedtelesis.com> | |
5 | */ | |
6 | ||
d678a59d | 7 | #include <common.h> |
691d719d | 8 | #include <init.h> |
5e6267af | 9 | #include <net.h> |
401d1c4f | 10 | #include <asm/global_data.h> |
cd93d625 | 11 | #include <linux/bitops.h> |
c05ed00a | 12 | #include <linux/delay.h> |
87a62bce CP |
13 | #include <linux/io.h> |
14 | #include <miiphy.h> | |
15 | #include <netdev.h> | |
d1471948 | 16 | #include <led.h> |
87a62bce CP |
17 | #include <asm/arch/cpu.h> |
18 | #include <asm/arch/soc.h> | |
19 | #include <asm/arch/mpp.h> | |
923d0a89 CP |
20 | #include <asm-generic/gpio.h> |
21 | #include <dm.h> | |
87a62bce CP |
22 | |
23 | /* Note: GPIO differences between specific boards | |
24 | * | |
25 | * We're trying to avoid having multiple build targets for all the Kirkwood | |
26 | * based boards one area where things tend to differ is GPIO usage. For the | |
27 | * most part the GPIOs driven by the bootloader are similar enough in function | |
28 | * that there is no harm in driving them. | |
29 | * | |
30 | * XZ4 XS6 XS16 GS24A GT40 GP24A GT24A | |
31 | * GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC | |
32 | */ | |
33 | ||
34 | #define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \ | |
35 | BIT(18) | BIT(17) | BIT(13) | BIT(12) | \ | |
36 | BIT(10)) | |
37 | #define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7)) | |
38 | #define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27)) | |
39 | #define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1)) | |
40 | ||
87a62bce CP |
41 | DECLARE_GLOBAL_DATA_PTR; |
42 | ||
87a62bce CP |
43 | int board_early_init_f(void) |
44 | { | |
45 | /* | |
46 | * default gpio configuration | |
47 | * There are maximum 64 gpios controlled through 2 sets of registers | |
48 | * the below configuration configures mainly initial LED status | |
49 | */ | |
50 | mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW, | |
51 | SBX81LIFKW_OE_VAL_HIGH, | |
52 | SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH); | |
53 | ||
54 | /* Multi-Purpose Pins Functionality configuration */ | |
55 | static const u32 kwmpp_config[] = { | |
56 | MPP0_SPI_SCn, | |
57 | MPP1_SPI_MOSI, | |
58 | MPP2_SPI_SCK, | |
59 | MPP3_SPI_MISO, | |
60 | MPP4_UART0_RXD, | |
61 | MPP5_UART0_TXD, | |
62 | MPP6_SYSRST_OUTn, | |
63 | MPP7_PEX_RST_OUTn, | |
64 | MPP8_TW_SDA, | |
65 | MPP9_TW_SCK, | |
66 | MPP10_GPO, | |
67 | MPP11_GPIO, | |
68 | MPP12_GPO, | |
69 | MPP13_GPIO, | |
70 | MPP14_GPIO, | |
71 | MPP15_UART0_RTS, | |
72 | MPP16_UART0_CTS, | |
73 | MPP17_GPIO, | |
74 | MPP18_GPO, | |
75 | MPP19_GPO, | |
76 | MPP20_GPIO, | |
77 | MPP21_GPIO, | |
78 | MPP22_GPIO, | |
79 | MPP23_GPIO, | |
80 | MPP24_GPIO, | |
81 | MPP25_GPIO, | |
82 | MPP26_GPIO, | |
83 | MPP27_GPIO, | |
84 | MPP28_GPIO, | |
85 | MPP29_GPIO, | |
86 | MPP30_GPIO, | |
87 | MPP31_GPIO, | |
88 | MPP32_GPIO, | |
89 | MPP33_GPIO, | |
90 | MPP34_GPIO, | |
91 | MPP35_GPIO, | |
92 | MPP36_GPIO, | |
93 | MPP37_GPIO, | |
94 | MPP38_GPIO, | |
95 | MPP39_GPIO, | |
96 | MPP40_GPIO, | |
97 | MPP41_GPIO, | |
98 | MPP42_GPIO, | |
99 | MPP43_GPIO, | |
100 | MPP44_GPIO, | |
101 | MPP45_GPIO, | |
102 | MPP46_GPIO, | |
103 | MPP47_GPIO, | |
104 | MPP48_GPIO, | |
105 | MPP49_GPIO, | |
106 | 0 | |
107 | }; | |
108 | ||
109 | kirkwood_mpp_conf(kwmpp_config, NULL); | |
110 | return 0; | |
111 | } | |
112 | ||
113 | int board_init(void) | |
114 | { | |
115 | /* Power-down unused subsystems. The required | |
116 | * subsystems are: | |
117 | * | |
118 | * GE0 b0 | |
119 | * PEX0 PHY b1 | |
120 | * PEX0.0 b2 | |
121 | * TSU b5 | |
122 | * SDRAM b6 | |
123 | * RUNIT b7 | |
124 | */ | |
125 | writel((BIT(0) | BIT(1) | BIT(2) | | |
126 | BIT(5) | BIT(6) | BIT(7)), | |
127 | KW_CPU_REG_BASE + 0x1c); | |
128 | ||
129 | /* address of boot parameters */ | |
130 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | |
131 | ||
87a62bce CP |
132 | return 0; |
133 | } | |
134 | ||
54e3316f CP |
135 | #ifdef CONFIG_RESET_PHY_R |
136 | /* automatically defined by kirkwood config.h */ | |
87a62bce | 137 | void reset_phy(void) |
54e3316f CP |
138 | { |
139 | } | |
140 | #endif | |
141 | ||
142 | #ifdef CONFIG_MV88E61XX_SWITCH | |
143 | int mv88e61xx_hw_reset(struct phy_device *phydev) | |
87a62bce | 144 | { |
923d0a89 CP |
145 | struct gpio_desc desc; |
146 | int ret; | |
147 | ||
148 | ret = dm_gpio_lookup_name("mvebu0_27", &desc); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
152 | ret = dm_gpio_request(&desc, "linkstreet_rst"); | |
153 | if (ret) | |
154 | return ret; | |
155 | ||
87a62bce CP |
156 | /* Ensure the 88e6097 gets at least 10ms Reset |
157 | */ | |
923d0a89 CP |
158 | dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); |
159 | dm_gpio_set_value(&desc, 0); | |
87a62bce | 160 | mdelay(20); |
923d0a89 | 161 | dm_gpio_set_value(&desc, 1); |
87a62bce | 162 | mdelay(20); |
54e3316f CP |
163 | |
164 | phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full; | |
165 | ||
166 | return 0; | |
87a62bce CP |
167 | } |
168 | #endif | |
169 | ||
170 | #ifdef CONFIG_MISC_INIT_R | |
171 | int misc_init_r(void) | |
172 | { | |
d1471948 CP |
173 | struct udevice *dev; |
174 | int ret; | |
175 | ||
176 | ret = led_get_by_label("status:ledp", &dev); | |
177 | if (!ret) | |
178 | led_set_state(dev, LEDST_ON); | |
179 | ||
180 | ret = led_get_by_label("status:ledn", &dev); | |
181 | if (!ret) | |
182 | led_set_state(dev, LEDST_OFF); | |
87a62bce CP |
183 | |
184 | return 0; | |
185 | } | |
186 | #endif |