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arm: socfpga: Split Altera socfpga into AV and CV SoCDK
[people/ms/u-boot.git] / board / altera / arria5-socdk / qts / pinmux_config.h
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1/* This file is generated by Preloader Generator */
2
3#ifndef _PRELOADER_PINMUX_CONFIG_H_
4#define _PRELOADER_PINMUX_CONFIG_H_
5
6/*
7 * State of enabling for which IP connected out through the muxing.
8 * Value 1 mean the IP connection is muxed out
9 */
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10#define CONFIG_HPS_EMAC0 (1)
11#define CONFIG_HPS_EMAC1 (0)
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12#define CONFIG_HPS_USB0 (0)
13#define CONFIG_HPS_USB1 (1)
14#define CONFIG_HPS_NAND (0)
15#define CONFIG_HPS_SDMMC (1)
a2d96abe 16#define CONFIG_HPS_QSPI (0)
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17#define CONFIG_HPS_UART0 (1)
18#define CONFIG_HPS_UART1 (0)
a2d96abe 19#define CONFIG_HPS_TRACE (0)
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20#define CONFIG_HPS_I2C0 (1)
21#define CONFIG_HPS_I2C1 (0)
22#define CONFIG_HPS_I2C2 (0)
23#define CONFIG_HPS_I2C3 (0)
a2d96abe 24#define CONFIG_HPS_SPIM0 (0)
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25#define CONFIG_HPS_SPIM1 (0)
26#define CONFIG_HPS_SPIS0 (0)
27#define CONFIG_HPS_SPIS1 (0)
28#define CONFIG_HPS_CAN0 (1)
29#define CONFIG_HPS_CAN1 (0)
30
31/* IP attribute value (which affected by pin muxing configuration) */
a2d96abe 32#define CONFIG_HPS_SDMMC_BUSWIDTH (8)
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33
34/* 1 if the pins are connected out */
a2d96abe 35#define CONFIG_HPS_QSPI_CS0 (0)
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36#define CONFIG_HPS_QSPI_CS1 (0)
37#define CONFIG_HPS_QSPI_CS2 (0)
38#define CONFIG_HPS_QSPI_CS3 (0)
39
40/* UART */
41/* 1 means the pin is mux out or available */
42#define CONFIG_HPS_UART0_TX (1)
43#define CONFIG_HPS_UART0_RX (1)
44#define CONFIG_HPS_UART0_CTS (0)
45#define CONFIG_HPS_UART0_RTS (0)
46#define CONFIG_HPS_UART1_TX (0)
47#define CONFIG_HPS_UART1_RX (0)
48#define CONFIG_HPS_UART1_CTS (0)
49#define CONFIG_HPS_UART1_RTS (0)
50
51/* Pin mux data */
52#define CONFIG_HPS_PINMUX_NUM (207)
53
54#endif /* _PRELOADER_PINMUX_CONFIG_H_ */