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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
3cb86f3e SR |
24 | /* define DEBUG for debugging output (obviously ;-)) */ |
25 | #if 0 | |
26 | #define DEBUG | |
27 | #endif | |
28 | ||
16c0cc1c SR |
29 | #include <common.h> |
30 | #include <asm/processor.h> | |
3cb86f3e SR |
31 | #include <asm/io.h> |
32 | #include <asm/gpio.h> | |
16c0cc1c | 33 | |
df8a24cd SR |
34 | extern void board_pll_init_f(void); |
35 | ||
c440bfe6 | 36 | #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
16c0cc1c SR |
37 | static void cram_bcr_write(u32 wr_val) |
38 | { | |
3cb86f3e | 39 | wr_val <<= 2; |
16c0cc1c | 40 | |
3cb86f3e | 41 | /* set CRAM_CRE to 1 */ |
6d0f6bcf | 42 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); |
16c0cc1c | 43 | |
3cb86f3e SR |
44 | /* Write BCR to CRAM on CS1 */ |
45 | out32(wr_val + 0x00200000, 0); | |
46 | debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000); | |
16c0cc1c | 47 | |
3cb86f3e SR |
48 | /* Write BCR to CRAM on CS2 */ |
49 | out32(wr_val + 0x02200000, 0); | |
50 | debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000); | |
16c0cc1c | 51 | |
3cb86f3e SR |
52 | sync(); |
53 | eieio(); | |
16c0cc1c | 54 | |
3cb86f3e | 55 | /* set CRAM_CRE back to 0 (normal operation) */ |
6d0f6bcf | 56 | gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); |
16c0cc1c | 57 | |
16c0cc1c SR |
58 | return; |
59 | } | |
c440bfe6 | 60 | #endif |
16c0cc1c | 61 | |
9973e3c6 | 62 | phys_size_t initdram(int board_type) |
16c0cc1c | 63 | { |
df8a24cd SR |
64 | #if defined(CONFIG_NAND_SPL) |
65 | u32 reg; | |
66 | ||
67 | /* don't reinit PLL when booting via I2C bootstrap option */ | |
68 | mfsdr(SDR_PINSTP, reg); | |
69 | if (reg != 0xf0000000) | |
70 | board_pll_init_f(); | |
71 | #endif | |
72 | ||
c440bfe6 SR |
73 | #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
74 | int i; | |
3cb86f3e | 75 | u32 val; |
16c0cc1c | 76 | |
3cb86f3e | 77 | /* 1. EBC need to program READY, CLK, ADV for ASync mode */ |
6d0f6bcf JCPV |
78 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); |
79 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); | |
80 | gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); | |
81 | gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); | |
16c0cc1c | 82 | |
3cb86f3e SR |
83 | /* 2. EBC in Async mode */ |
84 | mtebc(pb1ap, 0x078F1EC0); | |
85 | mtebc(pb2ap, 0x078F1EC0); | |
86 | mtebc(pb1cr, 0x000BC000); | |
87 | mtebc(pb2cr, 0x020BC000); | |
16c0cc1c | 88 | |
3cb86f3e SR |
89 | /* 3. Set CRAM in Sync mode */ |
90 | cram_bcr_write(0x7012); /* CRAM burst setting */ | |
16c0cc1c | 91 | |
3cb86f3e SR |
92 | /* 4. EBC in Sync mode */ |
93 | mtebc(pb1ap, 0x9C0201C0); | |
94 | mtebc(pb2ap, 0x9C0201C0); | |
16c0cc1c | 95 | |
3cb86f3e | 96 | /* Set GPIO pins back to alternate function */ |
6d0f6bcf JCPV |
97 | gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); |
98 | gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); | |
16c0cc1c | 99 | |
3cb86f3e SR |
100 | /* Config EBC to use RDY */ |
101 | mfsdr(sdrultra0, val); | |
c440bfe6 SR |
102 | mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); |
103 | ||
104 | /* Wait a short while, since for NAND booting this is too fast */ | |
105 | for (i=0; i<200000; i++) | |
106 | ; | |
107 | #endif | |
16c0cc1c | 108 | |
6d0f6bcf | 109 | return (CONFIG_SYS_MBYTES_RAM << 20); |
16c0cc1c | 110 | } |