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8e1a3fe5 SR |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <command.h> | |
27 | #include <i2c.h> | |
28 | #include <asm/io.h> | |
29 | ||
30 | /* | |
71665ebf | 31 | * NOR and NAND boot options change bytes 5, 6, 8, 9, 11. The |
8e1a3fe5 SR |
32 | * values are independent of the rest of the clock settings. |
33 | */ | |
34 | ||
35 | #define NAND_COMPATIBLE 0x01 | |
36 | #define NOR_COMPATIBLE 0x02 | |
37 | ||
38 | #define I2C_EEPROM_ADDR 0x52 | |
39 | ||
40 | static char *config_labels[] = { | |
41 | "CPU: 600 PLB: 200 OPB: 100 EBC: 100", | |
42 | "CPU: 800 PLB: 200 OPB: 100 EBC: 100", | |
43 | NULL | |
44 | }; | |
45 | ||
46 | static u8 boot_configs[][17] = { | |
47 | { | |
71665ebf | 48 | (NAND_COMPATIBLE | NOR_COMPATIBLE), |
8e1a3fe5 | 49 | 0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08, |
71665ebf | 50 | 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
8e1a3fe5 SR |
51 | }, |
52 | { | |
71665ebf | 53 | (NAND_COMPATIBLE | NOR_COMPATIBLE), |
8e1a3fe5 | 54 | 0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08, |
71665ebf | 55 | 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 |
8e1a3fe5 SR |
56 | }, |
57 | { | |
58 | 0, | |
59 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
60 | } | |
61 | }; | |
62 | ||
63 | /* | |
71665ebf | 64 | * Bytes 5,6,8,9,11 change for NAND boot |
8e1a3fe5 | 65 | */ |
499e7831 SR |
66 | #if 0 |
67 | /* | |
68 | * Values for 512 page size NAND chips, not used anymore, just | |
69 | * keep them here for reference | |
70 | */ | |
8e1a3fe5 | 71 | static u8 nand_boot[] = { |
71665ebf | 72 | 0x90, 0x01, 0xa0, 0x68, 0x58 |
8e1a3fe5 | 73 | }; |
499e7831 SR |
74 | #else |
75 | /* | |
76 | * Values for 2k page size NAND chips | |
77 | */ | |
78 | static u8 nand_boot[] = { | |
79 | 0x90, 0x01, 0xa0, 0xe8, 0x58 | |
80 | }; | |
81 | #endif | |
8e1a3fe5 SR |
82 | |
83 | static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
84 | { | |
85 | u8 *buf, b_nand; | |
86 | int x, y, nbytes, selcfg; | |
87 | extern char console_buffer[]; | |
88 | ||
89 | if (argc < 2) { | |
90 | printf("Usage:\n%s\n", cmdtp->usage); | |
91 | return 1; | |
92 | } | |
93 | ||
94 | if ((strcmp(argv[1], "nor") != 0) && | |
95 | (strcmp(argv[1], "nand") != 0)) { | |
96 | printf("Unsupported boot-device - only nor|nand support\n"); | |
97 | return 1; | |
98 | } | |
99 | ||
100 | /* set the nand flag based on provided input */ | |
101 | if ((strcmp(argv[1], "nand") == 0)) | |
102 | b_nand = 1; | |
103 | else | |
104 | b_nand = 0; | |
105 | ||
106 | printf("Available configurations: \n\n"); | |
107 | ||
108 | if (b_nand) { | |
109 | for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { | |
110 | /* filter on nand compatible */ | |
111 | if (boot_configs[x][0] & NAND_COMPATIBLE) { | |
112 | printf(" %d - %s\n", (y+1), config_labels[x]); | |
113 | y++; | |
114 | } | |
115 | } | |
116 | } else { | |
117 | for(x = 0, y = 0; boot_configs[x][0] != 0; x++) { | |
118 | /* filter on nor compatible */ | |
119 | if (boot_configs[x][0] & NOR_COMPATIBLE) { | |
120 | printf(" %d - %s\n", (y+1), config_labels[x]); | |
121 | y++; | |
122 | } | |
123 | } | |
124 | } | |
125 | ||
126 | do { | |
127 | nbytes = readline(" Selection [1-x / quit]: "); | |
128 | ||
129 | if (nbytes) { | |
130 | if (strcmp(console_buffer, "quit") == 0) | |
131 | return 0; | |
132 | selcfg = simple_strtol(console_buffer, NULL, 10); | |
133 | if ((selcfg < 1) || (selcfg > y)) | |
134 | nbytes = 0; | |
135 | } | |
136 | } while (nbytes == 0); | |
137 | ||
138 | ||
139 | y = (selcfg - 1); | |
140 | ||
141 | for (x = 0; boot_configs[x][0] != 0; x++) { | |
142 | if (b_nand) { | |
143 | if (boot_configs[x][0] & NAND_COMPATIBLE) { | |
144 | if (y > 0) | |
145 | y--; | |
146 | else if (y < 1) | |
147 | break; | |
148 | } | |
149 | } else { | |
150 | if (boot_configs[x][0] & NOR_COMPATIBLE) { | |
151 | if (y > 0) | |
152 | y--; | |
153 | else if (y < 1) | |
154 | break; | |
155 | } | |
156 | } | |
157 | } | |
158 | ||
159 | buf = &boot_configs[x][1]; | |
160 | ||
161 | if (b_nand) { | |
71665ebf SR |
162 | buf[5] = nand_boot[0]; |
163 | buf[6] = nand_boot[1]; | |
164 | buf[8] = nand_boot[2]; | |
165 | buf[9] = nand_boot[3]; | |
166 | buf[11] = nand_boot[4]; | |
8e1a3fe5 SR |
167 | } |
168 | ||
169 | if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0) | |
170 | printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR); | |
6d0f6bcf | 171 | udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); |
8e1a3fe5 SR |
172 | |
173 | printf("Done\n"); | |
174 | printf("Please power-cycle the board for the changes to take effect\n"); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | U_BOOT_CMD( | |
180 | bootstrap, 2, 0, do_bootstrap, | |
181 | "bootstrap - program the I2C bootstrap EEPROM\n", | |
182 | "<nand|nor> - strap to boot from NAND or NOR flash\n" | |
183 | ); |