[people/ms/u-boot.git] / board / amcc / canyonlands / canyonlands.c

/*
 * (C) Copyright 2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
#include <asm/gpio.h>

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	u32 sdr0_cust0;
	u32 pvr = get_pvr();

	/*------------------------------------------------------------------+
	 * Setup the interrupt controller polarities, triggers, etc.
	 *------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	mtdcr(uic2sr, 0xffffffff);	/* clear all */
	mtdcr(uic2er, 0x00000000);	/* disable all */
	mtdcr(uic2cr, 0x00000000);	/* all non-critical */
	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic2sr, 0xffffffff);	/* clear all */

	mtdcr(uic3sr, 0xffffffff);	/* clear all */
	mtdcr(uic3er, 0x00000000);	/* disable all */
	mtdcr(uic3cr, 0x00000000);	/* all non-critical */
	mtdcr(uic3pr, 0xffffffff);	/* per ref-board manual */
	mtdcr(uic3tr, 0x00000000);	/* per ref-board manual */
	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic3sr, 0xffffffff);	/* clear all */

	/* SDR Setting - enable NDFC */
	mfsdr(SDR0_CUST0, sdr0_cust0);
	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|
		SDR0_CUST0_NDFC_ENABLE		|
		SDR0_CUST0_NDFC_BW_8_BIT	|
		SDR0_CUST0_NDFC_ARE_MASK	|
		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
		(0x80000000 >> (28 + CFG_NAND_CS));
	mtsdr(SDR0_CUST0, sdr0_cust0);

	/*
	 * Configure PFC (Pin Function Control) registers
	 * UART0: 4 pins
	 */
	mtsdr(SDR0_PFC1, 0x00040000);

	/* Enable PCI host functionality in SDR0_PCI0 */
	mtsdr(SDR0_PCI0, 0xe0000000);

	/* Enable ethernet and take out of reset */
	out_8((void *)CFG_BCSR_BASE + 6, 0);

	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	out_8((void *)CFG_BCSR_BASE + 5, 0);

	/* Enable USB host & USB-OTG */
	out_8((void *)CFG_BCSR_BASE + 7, 0);

	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */

	/* Setup PLB4-AHB bridge based on the system address map */
	mtdcr(AHB_TOP, 0x8000004B);
	mtdcr(AHB_BOT, 0x8000004B);

	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
		/*
		 * Configure USB-STP pins as alternate and not GPIO
		 * It seems to be neccessary to configure the STP pins as GPIO
		 * input at powerup (perhaps while USB reset is asserted). So
		 * we configure those pins to their "real" function now.
		 */
		gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
		gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	}

	return 0;
}

int checkboard (void)
{
	char *s = getenv("serial#");
	u32 pvr = get_pvr();

	if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
		printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	else
		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*
 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 * board specific values.
 */
u32 ddr_wrdtr(u32 default_val) {
	return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}

u32 ddr_clktr(u32 default_val) {
	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}

#if defined(CONFIG_NAND_U_BOOT)
/*
 * NAND booting U-Boot version uses a fixed initialization, since the whole
 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
 * code.
 */
long int initdram(int board_type)
{
	return CFG_MBYTES_SDRAM << 20;
}
#endif

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*-------------------------------------------------------------------+
	 * Disable everything
	 *-------------------------------------------------------------------*/
	out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
	out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
	out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
	out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */

	/*-------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
	 * strapping options to not support sizes such as 128/256 MB.
	 *-------------------------------------------------------------------*/
	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
	out_le32((void *)PCIX0_PIM0LAH, 0);
	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
	out_le32((void *)PCIX0_BAR0, 0);

	/*-------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *-------------------------------------------------------------------*/
	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);

	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

#if defined(CONFIG_PCI)
/*
 * is_pci_host
 *
 * This routine is called to determine if a pci scan should be
 * performed. With various hardware environments (especially cPCI and
 * PPMC) it's insufficient to depend on the state of the arbiter enable
 * bit in the strap register, or generic host/adapter assumptions.
 *
 * Rather than hard-code a bad assumption in the general 440 code, the
 * 440 pci code requires the board to decide at runtime.
 *
 * Return 0 for adapter mode, non-zero for host (monarch) mode.
 */
int is_pci_host(struct pci_controller *hose)
{
	/* Board is always configured as host. */
	return (1);
}

static struct pci_controller pcie_hose[2] = {{0},{0}};

void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	int ret = 0;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 1; i++) {

		if (is_end_point(i))
			ret = ppc4xx_init_pcie_endport(i);
		else
			ret = ppc4xx_init_pcie_rootport(i);
		if (ret) {
			printf("PCIE%d: initialization as %s failed\n", i,
			       is_end_point(i) ? "endpoint" : "root-complex");
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMSIZE,
			       PCI_REGION_MEM);
		hose->region_count = 1;
		pci_register_hose(hose);

		if (is_end_point(i)) {
			ppc4xx_setup_pcie_endpoint(hose, i);
			/*
			 * Reson for no scanning is endpoint can not generate
			 * upstream configuration accesses.
			 */
		} else {
			ppc4xx_setup_pcie_rootpoint(hose, i);
			env = getenv ("pciscandelay");
			if (env != NULL) {
				delay = simple_strtoul(env, NULL, 10);
				if (delay > 5)
					printf("Warning, expect noticable delay before "
					       "PCIe scan due to 'pciscandelay' value!\n");
				mdelay(delay * 1000);
			}

			/*
			 * Config access can only go down stream
			 */
			hose->last_busno = pci_hose_scan(hose);
			bus = hose->last_busno + 1;
		}
	}
}
#endif /* CONFIG_PCI */

int board_early_init_r (void)
{
	/*
	 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
	 * boot EBC mapping only supports a maximum of 16MBytes
	 * (4.ff00.0000 - 4.ffff.ffff).
	 * To solve this problem, the FLASH has to get remapped to another
	 * EBC address which accepts bigger regions:
	 *
	 * 0xfc00.0000 -> 4.cc00.0000
	 */

	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
	mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
#else
	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
#endif

	/* Remove TLB entry of boot EBC mapping */
	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);

	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
		    TLB_WORD2_I_ENABLE);

	/*
	 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	 * 0xfc00.0000 is possible
	 */

	/*
	 * Clear potential errors resulting from auto-calibration.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return 0;
}

int misc_init_r(void)
{
	u32 sdr0_srst1 = 0;
	u32 eth_cfg;
	u32 pvr = get_pvr();

	/*
	 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	 * This is board specific, so let's do it here.
	 */
	mfsdr(SDR0_ETH_CFG, eth_cfg);
	/* disable SGMII mode */
	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
		     SDR0_ETH_CFG_SGMII1_ENABLE |
		     SDR0_ETH_CFG_SGMII0_ENABLE);
	/* Set the for 2 RGMII mode */
	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
	if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
		eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	else
		eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	mtsdr(SDR0_ETH_CFG, eth_cfg);

	/*
	 * The AHB Bridge core is held in reset after power-on or reset
	 * so enable it now
	 */
	mfsdr(SDR0_SRST1, sdr0_srst1);
	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	mtsdr(SDR0_SRST1, sdr0_srst1);

	return 0;
}

#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	u32 val[4];
	int rc;

	ft_cpu_setup(blob, bd);

	/* Fixup NOR mapping */
	val[0] = 0;				/* chip select number */
	val[1] = 0;				/* always 0 */
	val[2] = CFG_FLASH_BASE_PHYS_L;		/* we fixed up this address */
	val[3] = gd->bd->bi_flashsize;
	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
				  val, sizeof(val), 1);
	if (rc)
		printf("Unable to update property NOR mapping, err=%s\n",
		       fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
Commit	Line	Data
8e1a3fe5 SR	1	/*
	2	* (C) Copyright 2008
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20
	21	#include <common.h>
	22	#include <ppc440.h>
	23	#include <libfdt.h>
	24	#include <fdt_support.h>
	25	#include <asm/processor.h>
	26	#include <asm/io.h>
	27	#include <asm/mmu.h>
	28	#include <asm/4xx_pcie.h>
41712b4e	29	#include <asm/gpio.h>
8e1a3fe5 SR	30
	31	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
	35	int board_early_init_f(void)
	36	{
	37	u32 sdr0_cust0;
4c9e8557	38	u32 pvr = get_pvr();
8e1a3fe5 SR	39
	40	/*------------------------------------------------------------------+
	41	* Setup the interrupt controller polarities, triggers, etc.
	42	------------------------------------------------------------------/
	43	mtdcr(uic0sr, 0xffffffff); /* clear all */
	44	mtdcr(uic0er, 0x00000000); /* disable all */
	45	mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
	46	mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
	47	mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
	48	mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
	49	mtdcr(uic0sr, 0xffffffff); /* clear all */
	50
	51	mtdcr(uic1sr, 0xffffffff); /* clear all */
	52	mtdcr(uic1er, 0x00000000); /* disable all */
	53	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	54	mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
	55	mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
	56	mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
	57	mtdcr(uic1sr, 0xffffffff); /* clear all */
	58
	59	mtdcr(uic2sr, 0xffffffff); /* clear all */
	60	mtdcr(uic2er, 0x00000000); /* disable all */
	61	mtdcr(uic2cr, 0x00000000); /* all non-critical */
	62	mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
	63	mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
	64	mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
	65	mtdcr(uic2sr, 0xffffffff); /* clear all */
	66
	67	mtdcr(uic3sr, 0xffffffff); /* clear all */
	68	mtdcr(uic3er, 0x00000000); /* disable all */
	69	mtdcr(uic3cr, 0x00000000); /* all non-critical */
	70	mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
	71	mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
	72	mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
	73	mtdcr(uic3sr, 0xffffffff); /* clear all */
	74
	75	/* SDR Setting - enable NDFC */
	76	mfsdr(SDR0_CUST0, sdr0_cust0);
	77	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL \|
	78	SDR0_CUST0_NDFC_ENABLE \|
	79	SDR0_CUST0_NDFC_BW_8_BIT \|
	80	SDR0_CUST0_NDFC_ARE_MASK \|
	81	SDR0_CUST0_NDFC_BAC_ENCODE(3) \|
	82	(0x80000000 >> (28 + CFG_NAND_CS));
	83	mtsdr(SDR0_CUST0, sdr0_cust0);
	84
	85	/*
	86	* Configure PFC (Pin Function Control) registers
	87	* UART0: 4 pins
	88	*/
	89	mtsdr(SDR0_PFC1, 0x00040000);
	90
	91	/* Enable PCI host functionality in SDR0_PCI0 */
	92	mtsdr(SDR0_PCI0, 0xe0000000);
	93
	94	/* Enable ethernet and take out of reset */
	95	out_8((void *)CFG_BCSR_BASE + 6, 0);
	96
	97	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
	98	out_8((void *)CFG_BCSR_BASE + 5, 0);
	99
	100	/* Enable USB host & USB-OTG */
	101	out_8((void *)CFG_BCSR_BASE + 7, 0);
	102
103	mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
104
41712b4e SR	105	/* Setup PLB4-AHB bridge based on the system address map */
	106	mtdcr(AHB_TOP, 0x8000004B);
	107	mtdcr(AHB_BOT, 0x8000004B);
	108
4c9e8557 SR	109	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA)) {
	110	/*
	111	* Configure USB-STP pins as alternate and not GPIO
	112	* It seems to be neccessary to configure the STP pins as GPIO
	113	* input at powerup (perhaps while USB reset is asserted). So
	114	* we configure those pins to their "real" function now.
	115	*/
	116	gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	117	gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
	118	}
41712b4e	119
8e1a3fe5 SR	120	return 0;
	121	}
	122
	123	int checkboard (void)
	124	{
	125	char *s = getenv("serial#");
	126	u32 pvr = get_pvr();
	127
	128	if ((pvr == PVR_460GT_RA) \|\| (pvr == PVR_460GT_SE_RA))
	129	printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
	130	else
	131	printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
	132
	133	if (s != NULL) {
	134	puts(", serial# ");
	135	puts(s);
	136	}
	137	putc('\n');
	138
	139	return (0);
	140	}
	141
	142	/*
	143	* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
	144	* board specific values.
	145	*/
	146	u32 ddr_wrdtr(u32 default_val) {
	147	return (SDRAM_WRDTR_LLWP_1_CYC \| SDRAM_WRDTR_WTR_180_DEG_ADV \| 0x823);
	148	}
	149
	150	u32 ddr_clktr(u32 default_val) {
	151	return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
	152	}
	153
71665ebf SR	154	#if defined(CONFIG_NAND_U_BOOT)
	155	/*
	156	* NAND booting U-Boot version uses a fixed initialization, since the whole
	157	* I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
	158	* code.
	159	*/
	160	long int initdram(int board_type)
	161	{
	162	return CFG_MBYTES_SDRAM << 20;
	163	}
	164	#endif
	165
8e1a3fe5 SR	166	#if defined(CFG_DRAM_TEST)
	167	int testdram(void)
	168	{
	169	unsigned long mem = (unsigned long )0;
	170	const unsigned long kend = (1024 / sizeof(unsigned long));
	171	unsigned long k, n;
	172
	173	mtmsr(0);
	174
	175	for (k = 0; k < CFG_KBYTES_SDRAM;
	176	++k, mem += (1024 / sizeof(unsigned long))) {
	177	if ((k & 1023) == 0) {
	178	printf("%3d MB\r", k / 1024);
	179	}
	180
	181	memset(mem, 0xaaaaaaaa, 1024);
	182	for (n = 0; n < kend; ++n) {
	183	if (mem[n] != 0xaaaaaaaa) {
	184	printf("SDRAM test fails at: %08x\n",
	185	(uint) & mem[n]);
	186	return 1;
	187	}
	188	}
	189
	190	memset(mem, 0x55555555, 1024);
	191	for (n = 0; n < kend; ++n) {
	192	if (mem[n] != 0x55555555) {
	193	printf("SDRAM test fails at: %08x\n",
	194	(uint) & mem[n]);
	195	return 1;
	196	}
	197	}
	198	}
	199	printf("SDRAM test passes\n");
	200	return 0;
	201	}
	202	#endif
	203
	204	/*************************************************************************
	205	* pci_target_init
	206	*
	207	* The bootstrap configuration provides default settings for the pci
	208	* inbound map (PIM). But the bootstrap config choices are limited and
	209	* may not be sufficient for a given board.
	210	*
	211	************************************************************************/
	212	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
	213	void pci_target_init(struct pci_controller * hose )
	214	{
	215	/*-------------------------------------------------------------------+
	216	* Disable everything
	217	-------------------------------------------------------------------/
	218	out_le32((void )PCIX0_PIM0SA, 0); / disable */
	219	out_le32((void )PCIX0_PIM1SA, 0); / disable */
	220	out_le32((void )PCIX0_PIM2SA, 0); / disable */
	221	out_le32((void )PCIX0_EROMBA, 0); / disable expansion rom */
	222
	223	/*-------------------------------------------------------------------+
	224	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
	225	* strapping options to not support sizes such as 128/256 MB.
	226	-------------------------------------------------------------------/
	227	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
	228	out_le32((void *)PCIX0_PIM0LAH, 0);
	229	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1);
230	out_le32((void *)PCIX0_BAR0, 0);
231
232	/*-------------------------------------------------------------------+
233	* Program the board's subsystem id/vendor id
234	-------------------------------------------------------------------/
235	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
236	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
237
238	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY);
239	}
240	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
241
242	#if defined(CONFIG_PCI)
243	/*
244	* is_pci_host
245	*
246	* This routine is called to determine if a pci scan should be
247	* performed. With various hardware environments (especially cPCI and
248	* PPMC) it's insufficient to depend on the state of the arbiter enable
249	* bit in the strap register, or generic host/adapter assumptions.
250	*
251	* Rather than hard-code a bad assumption in the general 440 code, the
252	* 440 pci code requires the board to decide at runtime.
253	*
254	* Return 0 for adapter mode, non-zero for host (monarch) mode.
255	*/
256	int is_pci_host(struct pci_controller *hose)
257	{
258	/* Board is always configured as host. */
259	return (1);
260	}
261
262	static struct pci_controller pcie_hose[2] = {{0},{0}};
263
264	void pcie_setup_hoses(int busno)
265	{
266	struct pci_controller *hose;
267	int i, bus;
268	int ret = 0;
269	char *env;
270	unsigned int delay;
271
272	/*
273	* assume we're called after the PCIX hose is initialized, which takes
274	* bus ID 0 and therefore start numbering PCIe's from 1.
275	*/
276	bus = busno;
277	for (i = 0; i <= 1; i++) {
278
279	if (is_end_point(i))
280	ret = ppc4xx_init_pcie_endport(i);
281	else
282	ret = ppc4xx_init_pcie_rootport(i);
283	if (ret) {
284	printf("PCIE%d: initialization as %s failed\n", i,
285	is_end_point(i) ? "endpoint" : "root-complex");
286	continue;
287	}
288
289	hose = &pcie_hose[i];
290	hose->first_busno = bus;
291	hose->last_busno = bus;
292	hose->current_busno = bus;
293
294	/* setup mem resource */
295	pci_set_region(hose->regions + 0,
296	CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
297	CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
298	CFG_PCIE_MEMSIZE,
299	PCI_REGION_MEM);
300	hose->region_count = 1;
301	pci_register_hose(hose);
302
303	if (is_end_point(i)) {
304	ppc4xx_setup_pcie_endpoint(hose, i);
305	/*
306	* Reson for no scanning is endpoint can not generate
307	* upstream configuration accesses.
308	*/
309	} else {
310	ppc4xx_setup_pcie_rootpoint(hose, i);
311	env = getenv ("pciscandelay");
312	if (env != NULL) {
313	delay = simple_strtoul(env, NULL, 10);
314	if (delay > 5)
315	printf("Warning, expect noticable delay before "
316	"PCIe scan due to 'pciscandelay' value!\n");
317	mdelay(delay * 1000);
318	}
319
320	/*
321	* Config access can only go down stream
322	*/
323	hose->last_busno = pci_hose_scan(hose);
324	bus = hose->last_busno + 1;
325	}
326	}
327	}
328	#endif /* CONFIG_PCI */
329
330	int board_early_init_r (void)
331	{
332	/*
333	* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
334	* boot EBC mapping only supports a maximum of 16MBytes
335	* (4.ff00.0000 - 4.ffff.ffff).
336	* To solve this problem, the FLASH has to get remapped to another
337	* EBC address which accepts bigger regions:
338	*
339	* 0xfc00.0000 -> 4.cc00.0000
8e1a3fe5 SR	340	*/
	341
	342	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
71665ebf SR	343	#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
	344	mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L \| 0xda000);
	345	#else
8e1a3fe5	346	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L \| 0xda000);
71665ebf	347	#endif
8e1a3fe5 SR	348
	349	/* Remove TLB entry of boot EBC mapping */
	350	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
	351
	352	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
	353	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
	354	TLB_WORD2_I_ENABLE);
	355
	356	/*
	357	* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
	358	* 0xfc00.0000 is possible
	359	*/
	360
71665ebf SR	361	/*
	362	* Clear potential errors resulting from auto-calibration.
	363	* If not done, then we could get an interrupt later on when
	364	* exceptions are enabled.
	365	*/
	366	set_mcsr(get_mcsr());
	367
8e1a3fe5 SR	368	return 0;
	369	}
	370
	371	int misc_init_r(void)
	372	{
	373	u32 sdr0_srst1 = 0;
	374	u32 eth_cfg;
4c9e8557	375	u32 pvr = get_pvr();
8e1a3fe5 SR	376
	377	/*
	378	* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
	379	* This is board specific, so let's do it here.
	380	*/
	381	mfsdr(SDR0_ETH_CFG, eth_cfg);
	382	/* disable SGMII mode */
	383	eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE \|
	384	SDR0_ETH_CFG_SGMII1_ENABLE \|
	385	SDR0_ETH_CFG_SGMII0_ENABLE);
	386	/* Set the for 2 RGMII mode */
	387	/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
	388	eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
4c9e8557 SR	389	if ((pvr == PVR_460EX_RA) \|\| (pvr == PVR_460EX_SE_RA))
	390	eth_cfg \|= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
	391	else
	392	eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
8e1a3fe5 SR	393	mtsdr(SDR0_ETH_CFG, eth_cfg);
	394
	395	/*
	396	* The AHB Bridge core is held in reset after power-on or reset
	397	* so enable it now
	398	*/
	399	mfsdr(SDR0_SRST1, sdr0_srst1);
	400	sdr0_srst1 &= ~SDR0_SRST1_AHB;
	401	mtsdr(SDR0_SRST1, sdr0_srst1);
	402
	403	return 0;
	404	}
	405
	406	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
	407	void ft_board_setup(void blob, bd_t bd)
	408	{
	409	u32 val[4];
	410	int rc;
	411
	412	ft_cpu_setup(blob, bd);
	413
	414	/* Fixup NOR mapping */
	415	val[0] = 0; /* chip select number */
	416	val[1] = 0; /* always 0 */
d56a3ce1	417	val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
8e1a3fe5 SR	418	val[3] = gd->bd->bi_flashsize;
	419	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
	420	val, sizeof(val), 1);
	421	if (rc)
	422	printf("Unable to update property NOR mapping, err=%s\n",
	423	fdt_strerror(rc));
	424	}
	425	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */