projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e1a3fe5 SR |
1 | /* |
| 2 | * (C) Copyright 2008 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 8e1a3fe5 SR |
6 | */ |
| 7 | ||
| 25ddd1fb | 8 | #include <asm-offsets.h> |
| 8e1a3fe5 SR |
9 | #include <ppc_asm.tmpl> |
| 10 | #include <config.h> | |
| 61f2b38a | 11 | #include <asm/mmu.h> |
| 8e1a3fe5 SR |
12 | |
| 13 | /************************************************************************** | |
| 14 | * TLB TABLE | |
| 15 | * | |
| 16 | * This table is used by the cpu boot code to setup the initial tlb | |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 18 | * this table lets each board set things up however they like. | |
| 19 | * | |
| 20 | * Pointer to the table is returned in r1 | |
| 21 | * | |
| 22 | *************************************************************************/ | |
| 23 | .section .bootpg,"ax" | |
| 24 | .globl tlbtab | |
| 25 | ||
| 26 | tlbtab: | |
| 27 | tlbtab_start | |
| 28 | ||
| 29 | /* | |
| 30 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
| 31 | * use the speed up boot process. It is patched after relocation to | |
| 32 | * enable SA_I | |
| 33 | */ | |
| cf6eb6da | 34 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */ |
| 8e1a3fe5 SR |
35 | |
| 36 | /* | |
| 37 | * TLB entries for SDRAM are not needed on this platform. | |
| 38 | * They are dynamically generated in the SPD DDR(2) detection | |
| 39 | * routine. | |
| 40 | */ | |
| 41 | ||
| 6d0f6bcf | 42 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
| 8e1a3fe5 | 43 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
| cf6eb6da | 44 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G) |
| 8e1a3fe5 SR |
45 | #endif |
| 46 | ||
| cf6eb6da SR |
47 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
| 48 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG) | |
| 49 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
| 8e1a3fe5 | 50 | |
| cf6eb6da SR |
51 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) |
| 52 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) | |
| 53 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) | |
| 54 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) | |
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55 | |
| 56 | /* PCIe UTL register */ | |
| cf6eb6da | 57 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG) |
| 8e1a3fe5 | 58 | |
| f09f09d3 | 59 | #if !defined(CONFIG_ARCHES) |
| 8e1a3fe5 | 60 | /* TLB-entry for NAND */ |
| da7d3dff | 61 | tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG) |
| 8e1a3fe5 SR |
62 | |
| 63 | /* TLB-entry for CPLD */ | |
| cf6eb6da | 64 | tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG) |
| f09f09d3 AG |
65 | #else |
| 66 | /* TLB-entry for FPGA */ | |
| cf6eb6da | 67 | tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG) |
| f09f09d3 | 68 | #endif |
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69 | |
| 70 | /* TLB-entry for OCM */ | |
| cf6eb6da | 71 | tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I) |
| 8e1a3fe5 SR |
72 | |
| 73 | /* TLB-entry for Local Configuration registers => peripherals */ | |
| cf6eb6da | 74 | tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG) |
| 8e1a3fe5 | 75 | |
| 41712b4e | 76 | /* AHB: Internal USB Peripherals (USB, SATA) */ |
| cf6eb6da | 77 | tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG) |
| 41712b4e | 78 | |
| f09f09d3 | 79 | #if defined(CONFIG_RAPIDIO) |
| 3cbd8231 | 80 | /* TLB-entries for RapidIO (SRIO) */ |
| f09f09d3 | 81 | tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR, |
| cf6eb6da | 82 | 0xD, AC_RW | SA_IG) |
| f09f09d3 | 83 | tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR, |
| cf6eb6da | 84 | 0xD, AC_RW | SA_IG) |
| f09f09d3 | 85 | tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR, |
| cf6eb6da | 86 | 0xD, AC_RW | SA_IG) |
| f09f09d3 | 87 | tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000, |
| cf6eb6da | 88 | 0x4, AC_RW | SA_IG) |
| f09f09d3 AG |
89 | #endif |
| 90 | ||
| 8e1a3fe5 | 91 | tlbtab_end |