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c609719b WD |
1 | /* |
2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
1a459660 | 3 | * SPDX-License-Identifier: GPL-2.0+ |
c609719b WD |
4 | */ |
5 | ||
6 | #include <ppc_asm.tmpl> | |
7 | #include <config.h> | |
61f2b38a | 8 | #include <asm/mmu.h> |
550650dd | 9 | #include <asm/ppc4xx.h> |
c609719b WD |
10 | |
11 | /************************************************************************** | |
12 | * TLB TABLE | |
13 | * | |
14 | * This table is used by the cpu boot code to setup the initial tlb | |
15 | * entries. Rather than make broad assumptions in the cpu source tree, | |
16 | * this table lets each board set things up however they like. | |
17 | * | |
18 | * Pointer to the table is returned in r1 | |
19 | * | |
20 | *************************************************************************/ | |
21 | ||
8423e5e3 SR |
22 | .section .bootpg,"ax" |
23 | .globl tlbtab | |
c609719b WD |
24 | |
25 | tlbtab: | |
8423e5e3 SR |
26 | tlbtab_start |
27 | ||
cf6eb6da | 28 | tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
8423e5e3 SR |
29 | |
30 | /* | |
31 | * TLB entries for SDRAM are not needed on this platform. | |
32 | * They are dynamically generated in the SPD DDR(2) detection | |
33 | * routine. | |
34 | */ | |
35 | ||
cf6eb6da SR |
36 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) |
37 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX) | |
38 | tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX) | |
39 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG) | |
40 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG) | |
8423e5e3 | 41 | tlbtab_end |