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211ea91a SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
b36df561 SR |
25 | #include <asm/ppc4xx.h> |
26 | #include <asm/ppc405.h> | |
211ea91a SR |
27 | #include <libfdt.h> |
28 | #include <asm/processor.h> | |
09887762 | 29 | #include <asm/ppc4xx-gpio.h> |
ecdcbd4f | 30 | #include <asm/io.h> |
6eb3fb15 | 31 | #include <fdt_support.h> |
06dfaeef | 32 | #include <asm/errno.h> |
211ea91a SR |
33 | |
34 | #if defined(CONFIG_PCI) | |
35 | #include <pci.h> | |
36 | #include <asm/4xx_pcie.h> | |
37 | #endif | |
38 | ||
39 | DECLARE_GLOBAL_DATA_PTR; | |
40 | ||
6d0f6bcf | 41 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
211ea91a SR |
42 | |
43 | /* | |
44 | * Board early initialization function | |
45 | */ | |
46 | int board_early_init_f (void) | |
47 | { | |
7cfc12a7 SR |
48 | u32 val; |
49 | ||
211ea91a SR |
50 | /*--------------------------------------------------------------------+ |
51 | | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. | |
52 | +--------------------------------------------------------------------+ | |
53 | +---------------------------------------------------------------------+ | |
54 | |Interrupt| Source | Pol. | Sensi.| Crit. | | |
55 | +---------+-----------------------------------+-------+-------+-------+ | |
56 | | IRQ 00 | UART0 | High | Level | Non | | |
57 | | IRQ 01 | UART1 | High | Level | Non | | |
58 | | IRQ 02 | IIC0 | High | Level | Non | | |
59 | | IRQ 03 | TBD | High | Level | Non | | |
60 | | IRQ 04 | TBD | High | Level | Non | | |
61 | | IRQ 05 | EBM | High | Level | Non | | |
62 | | IRQ 06 | BGI | High | Level | Non | | |
63 | | IRQ 07 | IIC1 | Rising| Edge | Non | | |
64 | | IRQ 08 | SPI | High | Lvl/ed| Non | | |
65 | | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | | |
66 | | IRQ 10 | MAL TX EOB | High | Level | Non | | |
67 | | IRQ 11 | MAL RX EOB | High | Level | Non | | |
68 | | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | | |
69 | | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | | |
70 | | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | | |
71 | | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | | |
72 | | IRQ 16 | PCIE0 AL | high | Level | Non | | |
73 | | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | | |
74 | | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | | |
75 | | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | | |
76 | | IRQ 20 | PCIE0 TCR | High | Level | Non | | |
77 | | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | | |
78 | | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | | |
79 | | IRQ 23 | Security EIP-94 | High | Level | Non | | |
80 | | IRQ 24 | EMAC0 interrupt | High | Level | Non | | |
81 | | IRQ 25 | EMAC1 interrupt | High | Level | Non | | |
82 | | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | | |
83 | | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | | |
84 | | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | | |
85 | | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | | |
86 | | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | | |
87 | | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | | |
88 | |---------------------------------------------------------------------- | |
89 | | IRQ 32 | MAL Serr | High | Level | Non | | |
90 | | IRQ 33 | MAL Txde | High | Level | Non | | |
91 | | IRQ 34 | MAL Rxde | High | Level | Non | | |
92 | | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | | |
93 | | IRQ 36 | PCIE0 DCR Error | High | Level | Non | | |
94 | | IRQ 37 | EBC | High |Lvl Edg| Non | | |
95 | | IRQ 38 | NDFC | High | Level | Non | | |
96 | | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | | |
97 | | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | | |
98 | | IRQ 41 | PCIE1 AL | high | Level | Non | | |
99 | | IRQ 42 | PCIE1 VPD access | rising| edge | Non | | |
100 | | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | | |
101 | | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | | |
102 | | IRQ 45 | PCIE1 TCR | High | Level | Non | | |
103 | | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | | |
104 | | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | |
105 | | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | |
106 | | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | | |
107 | | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | | |
108 | | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | |
109 | | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | | |
110 | | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | | |
111 | | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | | |
112 | | IRQ 55 | Serial ROM | High | Level | Non | | |
113 | | IRQ 56 | GPT Decrement Pulse | High | Level | Non | | |
114 | | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | | |
115 | | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | | |
116 | | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | | |
117 | | IRQ 60 | EMAC0 Wake-up | High | Level | Non | | |
118 | | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | | |
119 | | IRQ 62 | EMAC1 Wake-up | High | Level | Non | | |
120 | |---------------------------------------------------------------------- | |
121 | | IRQ 64 | PE0 AL | High | Level | Non | | |
122 | | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | |
123 | | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | |
124 | | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | |
125 | | IRQ 68 | PE0 TCR | High | Level | Non | | |
126 | | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | |
127 | | IRQ 70 | PE0 DCR Error | High | Level | Non | | |
128 | | IRQ 71 | Reserved | N/A | N/A | Non | | |
129 | | IRQ 72 | PE1 AL | High | Level | Non | | |
130 | | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | |
131 | | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | |
132 | | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | |
133 | | IRQ 76 | PE1 TCR | High | Level | Non | | |
134 | | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | |
135 | | IRQ 78 | PE1 DCR Error | High | Level | Non | | |
136 | | IRQ 79 | Reserved | N/A | N/A | Non | | |
137 | | IRQ 80 | PE2 AL | High | Level | Non | | |
138 | | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | |
139 | | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | |
140 | | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | |
141 | | IRQ 84 | PE2 TCR | High | Level | Non | | |
142 | | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | |
143 | | IRQ 86 | PE2 DCR Error | High | Level | Non | | |
144 | | IRQ 87 | Reserved | N/A | N/A | Non | | |
145 | | IRQ 88 | External IRQ(5) | Progr | Progr | Non | | |
146 | | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | |
147 | | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | |
148 | | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | |
149 | | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | |
150 | | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | |
151 | | IRQ 94 | Reserved | N/A | N/A | Non | | |
152 | | IRQ 95 | Reserved | N/A | N/A | Non | | |
153 | |--------------------------------------------------------------------- | |
154 | +---------+-----------------------------------+-------+-------+------*/ | |
155 | /*--------------------------------------------------------------------+ | |
156 | | Initialise UIC registers. Clear all interrupts. Disable all | |
157 | | interrupts. | |
158 | | Set critical interrupt values. Set interrupt polarities. Set | |
159 | | interrupt trigger levels. Make bit 0 High priority. Clear all | |
160 | | interrupts again. | |
161 | +-------------------------------------------------------------------*/ | |
162 | ||
952e7760 SR |
163 | mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ |
164 | mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ | |
165 | mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ | |
166 | mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ | |
167 | mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ | |
168 | mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
169 | mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ | |
170 | mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ | |
211ea91a | 171 | |
952e7760 SR |
172 | mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ |
173 | mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ | |
174 | mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ | |
175 | mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ | |
176 | mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ | |
177 | mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
178 | mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ | |
179 | mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ | |
211ea91a | 180 | |
952e7760 SR |
181 | mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ |
182 | mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ | |
211ea91a | 183 | /* Except cascade UIC0 and UIC1 */ |
952e7760 SR |
184 | mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ |
185 | mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ | |
186 | mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ | |
187 | mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
188 | mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ | |
189 | mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ | |
211ea91a SR |
190 | |
191 | /* | |
192 | * Note: Some cores are still in reset when the chip starts, so | |
193 | * take them out of reset | |
194 | */ | |
195 | mtsdr(SDR0_SRST, 0); | |
196 | ||
ecdcbd4f | 197 | /* Reset PCIe slots */ |
6d0f6bcf | 198 | gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0); |
ecdcbd4f | 199 | udelay(100); |
6d0f6bcf | 200 | gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1); |
ecdcbd4f | 201 | |
7cfc12a7 SR |
202 | /* |
203 | * Configure PFC (Pin Function Control) registers | |
204 | * -> Enable USB | |
205 | */ | |
206 | val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; | |
207 | mtsdr(SDR0_PFC1, val); | |
208 | ||
211ea91a SR |
209 | return 0; |
210 | } | |
211 | ||
212 | int misc_init_r(void) | |
213 | { | |
5a1aceb0 | 214 | #ifdef CONFIG_ENV_IS_IN_FLASH |
211ea91a SR |
215 | /* Monitor protection ON by default */ |
216 | flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 217 | -CONFIG_SYS_MONITOR_LEN, |
211ea91a SR |
218 | 0xffffffff, |
219 | &flash_info[0]); | |
220 | #endif | |
221 | ||
222 | return 0; | |
223 | } | |
224 | ||
225 | int checkboard (void) | |
226 | { | |
f0c0b3a9 WD |
227 | char buf[64]; |
228 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
211ea91a SR |
229 | |
230 | printf("Board: Makalu - AMCC PPC405EX Evaluation Board"); | |
231 | ||
f0c0b3a9 | 232 | if (i > 0) { |
211ea91a | 233 | puts(", serial# "); |
f0c0b3a9 | 234 | puts(buf); |
211ea91a SR |
235 | } |
236 | putc('\n'); | |
237 | ||
238 | return (0); | |
239 | } |