[people/ms/u-boot.git] / board / amcc / ocotea / ocotea.c

/*
 *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include "ocotea.h"
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>

DECLARE_GLOBAL_DATA_PTR;

#define BOOT_SMALL_FLASH	32	/* 00100000 */
#define FLASH_ONBD_N		2	/* 00000010 */
#define FLASH_SRAM_SEL		1	/* 00000001 */

long int fixed_sdram (void);
void fpga_init (void);

int board_early_init_f (void)
{
	unsigned long mfr;
	unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
	unsigned char switch_status;
	unsigned long cs0_base;
	unsigned long cs0_size;
	unsigned long cs0_twt;
	unsigned long cs2_base;
	unsigned long cs2_size;
	unsigned long cs2_twt;

	/*-------------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------------*/
	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/* read FPGA base register FPGA_REG0 */
	switch_status = *fpga_base;

	if (switch_status & 0x40) {
		cs0_base = 0xFFE00000;
		cs0_size = EBC_BXCR_BS_2MB;
		cs0_twt = 8;
		cs2_base = 0xFF800000;
		cs2_size = EBC_BXCR_BS_4MB;
		cs2_twt = 10;
	} else {
		cs0_base = 0xFFC00000;
		cs0_size = EBC_BXCR_BS_4MB;
		cs0_twt = 10;
		cs2_base = 0xFF800000;
		cs2_size = EBC_BXCR_BS_2MB;
		cs2_twt = 8;
	}

	/*-------------------------------------------------------------------------+
	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | 4 MB FLASH. Initialize bank 2 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
	      EBC_BXAP_BCE_DISABLE|
	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
	      EBC_BXAP_BEM_WRITEONLY|
	      EBC_BXAP_PEN_DISABLED);
	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	/*
	 * Because of the interrupt handling rework to handle 440GX interrupts
	 * with the common code, we needed to change names of the UIC registers.
	 * Here the new relationship:
	 *
	 * U-Boot name	440GX name
	 * -----------------------
	 * UIC0		UICB0
	 * UIC1		UIC0
	 * UIC2		UIC1
	 * UIC3		UIC2
	 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
	mtdcr (UIC1ER, 0x00000000);	/* disable all */
	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (UIC1PR, 0xfffffe13);	/* per ref-board manual */
	mtdcr (UIC1TR, 0x01c00008);	/* per ref-board manual */
	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */

	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
	mtdcr (UIC2ER, 0x00000000);	/* disable all */
	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC2SR, 0xffffffff);	/* clear all */

	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
	mtdcr (UIC3ER, 0x00000000);	/* disable all */
	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC3SR, 0xffffffff);	/* clear all */

	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	mtdcr (UIC0ER, 0x00000000); /* disable all */
	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	mtdcr (UIC0PR, 0xfc000000); /* */
	mtdcr (UIC0TR, 0x00000000); /* */
	mtdcr (UIC0VR, 0x00000001); /* */
	mfsdr (SDR0_MFR, mfr);
	mfr &= ~SDR0_MFR_ECS_MASK;
/*	mtsdr(SDR0_MFR, mfr); */
	fpga_init();

	return 0;
}


int checkboard (void)
{
	char *s = getenv ("serial#");

	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
	if (s != NULL) {
		puts (", serial# ");
		puts (s);
	}
	putc ('\n');

	return (0);
}


phys_size_t initdram (int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram ();
#else
	dram_size = fixed_sdram ();
#endif
	return dram_size;
}


#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 *
 *  Assumes:    128 MB, non-ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
long int fixed_sdram (void)
{
	uint reg;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram (SDRAM0_UABBA, 0x00000000);	/* ubba=0 (default)             */
	mtsdram (SDRAM0_SLIO, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */
	mtsdram (SDRAM0_DEVOPT, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram (SDRAM0_WDDCTR, 0x00000000);	/* wrcp=0 dcd=0                 */
	mtsdram (SDRAM0_CLKTR, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram (SDRAM0_B0CR, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram (SDRAM0_TR0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
	/* RA=10 RD=3                       */
	mtsdram (SDRAM0_TR1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
	mtsdram (SDRAM0_RTR, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
	mtsdram (SDRAM0_CFG1, 0x00000000);	/* Self-refresh exit, disable PM    */
	udelay (400);			/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram (SDRAM0_CFG0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
	for (;;) {
		mfsdram (SDRAM0_MCSTS, reg);
		if (reg & 0x80000000)
			break;
	}

	return (128 * 1024 * 1024);	/* 128 MB                           */
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */


/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 *	The ocotea board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(SDR0_SDSTP1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	return 1;
}
#endif /* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r( PCIL0_PIM0SA, 0 ); /* disable */
	out32r( PCIL0_PIM1SA, 0 ); /* disable */
	out32r( PCIL0_PIM2SA, 0 ); /* disable */
	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	 * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
	out32r( PCIL0_PIM0LAH, 0 );
	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );

	out32r( PCIL0_BAR0, 0 );

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );

	out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */


void fpga_init(void)
{
	unsigned long group;
	unsigned long sdr0_pfc0;
	unsigned long sdr0_pfc1;
	unsigned long sdr0_cust0;
	unsigned long pvr;

	mfsdr (SDR0_PFC0, sdr0_pfc0);
	mfsdr (SDR0_PFC1, sdr0_pfc1);
	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
	pvr = get_pvr ();

	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
	if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
		sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
		out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
		     FPGA_REG2_EXT_INTFACE_ENABLE);
		mtsdr (SDR0_PFC0, sdr0_pfc0);
		mtsdr (SDR0_PFC1, sdr0_pfc1);
	} else {
		sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
		switch (group)
		{
		case 0:
		case 1:
		case 2:
			/* CPU trace A */
			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
			     FPGA_REG2_EXT_INTFACE_ENABLE);
			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
			mtsdr (SDR0_PFC0, sdr0_pfc0);
			mtsdr (SDR0_PFC1, sdr0_pfc1);
			break;
		case 3:
		case 4:
		case 5:
		case 6:
			/* CPU trace B - Over EBMI */
			sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
			mtsdr (SDR0_PFC0, sdr0_pfc0);
			mtsdr (SDR0_PFC1, sdr0_pfc1);
			out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
			     FPGA_REG2_EXT_INTFACE_DISABLE);
			break;
		}
	}

	/* Initialize the ethernet specific functions in the fpga */
	mfsdr(SDR0_PFC1, sdr0_pfc1);
	mfsdr(SDR0_CUST0, sdr0_cust0);
	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
	    ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
	     (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
			     FPGA_REG3_ENET_GROUP7);
		}
		else
		{
			if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
			{
				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
				     FPGA_REG3_ENET_GROUP7);
			}
			else
			{
				out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
				     FPGA_REG3_ENET_GROUP8);
			}
		}
	}
	else
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
			     FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
		}
		else
		{
			out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
			     FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
		}
	}
	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
	     FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
	     FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);

	/* reset the gigabyte phy if necessary */
	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
	{
		if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
		{
			out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
			udelay(10000);
			out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
		}
		else
		{
			out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
			udelay(10000);
			out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
		}
	}

	/*
	 * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
	 */
	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
		out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
		udelay(10000);
		out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
	}

	/* Turn off the LED's */
	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
	     FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
	     FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);

	return;
}

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{

	return (ctrlc());
}
#endif
Commit	Line	Data
0e6d798c WD	1	/*
	2	* Copyright (C) 2004 PaulReynolds@lhsolutions.com
	3	*
8a316c9b SR	4	* (C) Copyright 2005
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
0e6d798c WD	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26
	27	#include <common.h>
	28	#include "ocotea.h"
	29	#include <asm/processor.h>
	30	#include <spd_sdram.h>
d6c61aab	31	#include <ppc4xx_enet.h>
0e6d798c	32
d87080b7 WD	33	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	34
0e6d798c WD	35	#define BOOT_SMALL_FLASH 32 /* 00100000 */
	36	#define FLASH_ONBD_N 2 /* 00000010 */
	37	#define FLASH_SRAM_SEL 1 /* 00000001 */
	38
	39	long int fixed_sdram (void);
	40	void fpga_init (void);
	41
	42	int board_early_init_f (void)
	43	{
4b248f3f	44	unsigned long mfr;
6d0f6bcf	45	unsigned char fpga_base = (unsigned char ) CONFIG_SYS_FPGA_BASE;
7ec25502 SR	46	unsigned char switch_status;
	47	unsigned long cs0_base;
	48	unsigned long cs0_size;
	49	unsigned long cs0_twt;
	50	unsigned long cs2_base;
	51	unsigned long cs2_size;
	52	unsigned long cs2_twt;
	53
0e6d798c WD	54	/*-------------------------------------------------------------------------+
	55	\| Initialize EBC CONFIG
	56	+-------------------------------------------------------------------------*/
d1c3b275	57	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK \|
0e6d798c WD	58	EBC_CFG_PTD_ENABLE \| EBC_CFG_RTC_64PERCLK \|
	59	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	60	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_NONDEFAULT \|
	61	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
	62
7ec25502 SR	63	/*-------------------------------------------------------------------------+
	64	\| FPGA. Initialize bank 7 with default values.
	65	+-------------------------------------------------------------------------*/
d1c3b275	66	mtebc(PB7AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(7)\|
7ec25502 SR	67	EBC_BXAP_BCE_DISABLE\|
	68	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	69	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	70	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	71	EBC_BXAP_BEM_WRITEONLY\|
	72	EBC_BXAP_PEN_DISABLED);
d1c3b275	73	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)\|
7ec25502 SR	74	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	75
	76	/* read FPGA base register FPGA_REG0 */
	77	switch_status = *fpga_base;
	78
	79	if (switch_status & 0x40) {
	80	cs0_base = 0xFFE00000;
	81	cs0_size = EBC_BXCR_BS_2MB;
	82	cs0_twt = 8;
	83	cs2_base = 0xFF800000;
	84	cs2_size = EBC_BXCR_BS_4MB;
	85	cs2_twt = 10;
	86	} else {
	87	cs0_base = 0xFFC00000;
	88	cs0_size = EBC_BXCR_BS_4MB;
	89	cs0_twt = 10;
	90	cs2_base = 0xFF800000;
	91	cs2_size = EBC_BXCR_BS_2MB;
	92	cs2_twt = 8;
	93	}
	94
0e6d798c WD	95	/*-------------------------------------------------------------------------+
	96	\| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
	97	+-------------------------------------------------------------------------*/
d1c3b275	98	mtebc(PB0AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(cs0_twt)\|
0e6d798c WD	99	EBC_BXAP_BCE_DISABLE\|
	100	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	101	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	102	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	103	EBC_BXAP_BEM_WRITEONLY\|
	104	EBC_BXAP_PEN_DISABLED);
d1c3b275	105	mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)\|
7ec25502	106	cs0_size\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
0e6d798c WD	107
	108	/*-------------------------------------------------------------------------+
	109	\| 8KB NVRAM/RTC. Initialize bank 1 with default values.
	110	+-------------------------------------------------------------------------*/
d1c3b275	111	mtebc(PB1AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(10)\|
0e6d798c WD	112	EBC_BXAP_BCE_DISABLE\|
	113	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	114	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	115	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	116	EBC_BXAP_BEM_WRITEONLY\|
	117	EBC_BXAP_PEN_DISABLED);
d1c3b275	118	mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)\|
0e6d798c WD	119	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	120
	121	/*-------------------------------------------------------------------------+
	122	\| 4 MB FLASH. Initialize bank 2 with default values.
	123	+-------------------------------------------------------------------------*/
d1c3b275	124	mtebc(PB2AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(cs2_twt)\|
0e6d798c WD	125	EBC_BXAP_BCE_DISABLE\|
	126	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	127	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	128	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	129	EBC_BXAP_BEM_WRITEONLY\|
	130	EBC_BXAP_PEN_DISABLED);
d1c3b275	131	mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)\|
7ec25502	132	cs2_size\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
0e6d798c WD	133
	134	/*-------------------------------------------------------------------------+
	135	\| FPGA. Initialize bank 7 with default values.
	136	+-------------------------------------------------------------------------*/
d1c3b275	137	mtebc(PB7AP, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(7)\|
0e6d798c WD	138	EBC_BXAP_BCE_DISABLE\|
	139	EBC_BXAP_CSN_ENCODE(1)\|EBC_BXAP_OEN_ENCODE(1)\|
	140	EBC_BXAP_WBN_ENCODE(1)\|EBC_BXAP_WBF_ENCODE(1)\|
	141	EBC_BXAP_TH_ENCODE(1)\|EBC_BXAP_RE_DISABLED\|
	142	EBC_BXAP_BEM_WRITEONLY\|
	143	EBC_BXAP_PEN_DISABLED);
d1c3b275	144	mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)\|
0e6d798c WD	145	EBC_BXCR_BS_1MB\|EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	146
	147	/*--------------------------------------------------------------------
	148	* Setup the interrupt controller polarities, triggers, etc.
	149	-------------------------------------------------------------------/
5de85140 SR	150	/*
	151	* Because of the interrupt handling rework to handle 440GX interrupts
	152	* with the common code, we needed to change names of the UIC registers.
	153	* Here the new relationship:
	154	*
	155	* U-Boot name 440GX name
	156	* -----------------------
	157	* UIC0 UICB0
	158	* UIC1 UIC0
	159	* UIC2 UIC1
	160	* UIC3 UIC2
	161	*/
952e7760 SR	162	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	163	mtdcr (UIC1ER, 0x00000000); /* disable all */
	164	mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
	165	mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
	166	mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
	167	mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
	168	mtdcr (UIC1SR, 0xffffffff); /* clear all */
	169
	170	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	171	mtdcr (UIC2ER, 0x00000000); /* disable all */
	172	mtdcr (UIC2CR, 0x00000000); /* all non-critical */
	173	mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
	174	mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
	175	mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
	176	mtdcr (UIC2SR, 0xffffffff); /* clear all */
	177
	178	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	179	mtdcr (UIC3ER, 0x00000000); /* disable all */
	180	mtdcr (UIC3CR, 0x00000000); /* all non-critical */
	181	mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
	182	mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
	183	mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
	184	mtdcr (UIC3SR, 0xffffffff); /* clear all */
	185
	186	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	187	mtdcr (UIC0ER, 0x00000000); /* disable all */
	188	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	189	mtdcr (UIC0PR, 0xfc000000); /* */
	190	mtdcr (UIC0TR, 0x00000000); /* */
	191	mtdcr (UIC0VR, 0x00000001); /* */
d1c3b275	192	mfsdr (SDR0_MFR, mfr);
4b248f3f	193	mfr &= ~SDR0_MFR_ECS_MASK;
d1c3b275	194	/* mtsdr(SDR0_MFR, mfr); */
0e6d798c WD	195	fpga_init();
	196
	197	return 0;
	198	}
	199
	200
	201	int checkboard (void)
	202	{
77ddac94	203	char *s = getenv ("serial#");
0e6d798c	204
8a316c9b SR	205	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
	206	if (s != NULL) {
	207	puts (", serial# ");
	208	puts (s);
	209	}
	210	putc ('\n');
	211
0e6d798c WD	212	return (0);
	213	}
	214
	215
9973e3c6	216	phys_size_t initdram (int board_type)
0e6d798c WD	217	{
	218	long dram_size = 0;
	219
	220	#if defined(CONFIG_SPD_EEPROM)
d87080b7	221	dram_size = spd_sdram ();
0e6d798c WD	222	#else
	223	dram_size = fixed_sdram ();
	224	#endif
	225	return dram_size;
	226	}
	227
	228
0e6d798c WD	229	#if !defined(CONFIG_SPD_EEPROM)
	230	/*************************************************************************
	231	* fixed sdram init -- doesn't use serial presence detect.
	232	*
	233	* Assumes: 128 MB, non-ECC, non-registered
	234	* PLB @ 133 MHz
	235	*
	236	************************************************************************/
	237	long int fixed_sdram (void)
	238	{
	239	uint reg;
	240
	241	/*--------------------------------------------------------------------
	242	* Setup some default
	243	------------------------------------------------------------------/
95b602ba SR	244	mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
	245	mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	246	mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
	247	mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
	248	mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
0e6d798c WD	249
	250	/*--------------------------------------------------------------------
	251	* Setup for board-specific specific mem
	252	------------------------------------------------------------------/
	253	/*
	254	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	255	*/
95b602ba SR	256	mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
95b602ba SR	257	mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
0e6d798c	258	/* RA=10 RD=3 */
95b602ba SR	259	mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
	260	mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
	261	mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
0e6d798c WD	262	udelay (400); /* Delay 200 usecs (min) */
	263
	264	/*--------------------------------------------------------------------
	265	* Enable the controller, then wait for DCEN to complete
	266	------------------------------------------------------------------/
95b602ba	267	mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
0e6d798c	268	for (;;) {
95b602ba	269	mfsdram (SDRAM0_MCSTS, reg);
0e6d798c WD	270	if (reg & 0x80000000)
	271	break;
	272	}
	273
	274	return (128 * 1024 * 1024); /* 128 MB */
	275	}
	276	#endif /* !defined(CONFIG_SPD_EEPROM) */
	277
	278
	279	/*************************************************************************
	280	* pci_pre_init
	281	*
	282	* This routine is called just prior to registering the hose and gives
	283	* the board the opportunity to check things. Returning a value of zero
	284	* indicates that things are bad & PCI initialization should be aborted.
	285	*
	286	* Different boards may wish to customize the pci controller structure
	287	* (add regions, override default access routines, etc) or perform
	288	* certain pre-initialization actions.
	289	*
	290	************************************************************************/
466fff1a	291	#if defined(CONFIG_PCI)
0e6d798c WD	292	int pci_pre_init(struct pci_controller * hose )
	293	{
	294	unsigned long strap;
	295
	296	/*--------------------------------------------------------------------------+
	297	* The ocotea board is always configured as the host & requires the
	298	* PCI arbiter to be enabled.
	299	--------------------------------------------------------------------------/
d1c3b275	300	mfsdr(SDR0_SDSTP1, strap);
0e6d798c WD	301	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
	302	printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
	303	return 0;
	304	}
	305
	306	return 1;
	307	}
466fff1a	308	#endif /* defined(CONFIG_PCI) */
0e6d798c WD	309
	310	/*************************************************************************
	311	* pci_target_init
	312	*
	313	* The bootstrap configuration provides default settings for the pci
	314	* inbound map (PIM). But the bootstrap config choices are limited and
	315	* may not be sufficient for a given board.
	316	*
	317	************************************************************************/
6d0f6bcf	318	#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
0e6d798c WD	319	void pci_target_init(struct pci_controller * hose )
0e6d798c WD	320	{
0e6d798c WD	321	/*--------------------------------------------------------------------------+
	322	* Disable everything
	323	--------------------------------------------------------------------------/
ddc922ff NG	324	out32r( PCIL0_PIM0SA, 0 ); /* disable */
	325	out32r( PCIL0_PIM1SA, 0 ); /* disable */
	326	out32r( PCIL0_PIM2SA, 0 ); /* disable */
	327	out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
0e6d798c WD	328
	329	/*--------------------------------------------------------------------------+
	330	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	331	* options to not support sizes such as 128/256 MB.
	332	--------------------------------------------------------------------------/
ddc922ff NG	333	out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
	334	out32r( PCIL0_PIM0LAH, 0 );
	335	out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) \| 1 );
0e6d798c	336
ddc922ff	337	out32r( PCIL0_BAR0, 0 );
0e6d798c WD	338
	339	/*--------------------------------------------------------------------------+
	340	* Program the board's subsystem id/vendor id
	341	--------------------------------------------------------------------------/
ddc922ff NG	342	out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
ddc922ff NG	343	out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
0e6d798c	344
ddc922ff	345	out16r( PCIL0_CMD, in16r(PCIL0_CMD) \| PCI_COMMAND_MEMORY );
0e6d798c	346	}
6d0f6bcf	347	#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
0e6d798c WD	348
0e6d798c WD	349
0e6d798c WD	350	void fpga_init(void)
	351	{
	352	unsigned long group;
	353	unsigned long sdr0_pfc0;
	354	unsigned long sdr0_pfc1;
	355	unsigned long sdr0_cust0;
	356	unsigned long pvr;
	357
d1c3b275 SR	358	mfsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	359	mfsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	360	group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
	361	pvr = get_pvr ();
	362
	363	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) \| SDR0_PFC0_GEIE_TRE;
	364	if ( ((pvr == PVR_440GX_RA) \|\| (pvr == PVR_440GX_RB)) && ((group == 4) \|\| (group == 5))) {
	365	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) \| SDR0_PFC0_TRE_DISABLE;
	366	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_EMS;
	367	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	368	FPGA_REG2_EXT_INTFACE_ENABLE);
d1c3b275 SR	369	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	370	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	371	} else {
	372	sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) \| SDR0_PFC0_TRE_ENABLE;
	373	switch (group)
	374	{
	375	case 0:
	376	case 1:
	377	case 2:
	378	/* CPU trace A */
	379	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	380	FPGA_REG2_EXT_INTFACE_ENABLE);
	381	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_EMS;
d1c3b275 SR	382	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	383	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	384	break;
	385	case 3:
	386	case 4:
	387	case 5:
	388	case 6:
	389	/* CPU trace B - Over EBMI */
	390	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) \| SDR0_PFC1_CTEMS_CPUTRACE;
d1c3b275 SR	391	mtsdr (SDR0_PFC0, sdr0_pfc0);
d1c3b275 SR	392	mtsdr (SDR0_PFC1, sdr0_pfc1);
0e6d798c WD	393	out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) \|
	394	FPGA_REG2_EXT_INTFACE_DISABLE);
	395	break;
	396	}
	397	}
	398
	399	/* Initialize the ethernet specific functions in the fpga */
d1c3b275 SR	400	mfsdr(SDR0_PFC1, sdr0_pfc1);
d1c3b275 SR	401	mfsdr(SDR0_CUST0, sdr0_cust0);
0e6d798c WD	402	if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
	403	((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) \|\|
	404	(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
	405	{
	406	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	407	{
	408	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) \|
	409	FPGA_REG3_ENET_GROUP7);
	410	}
	411	else
	412	{
	413	if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
	414	{
	415	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	416	FPGA_REG3_ENET_GROUP7);
	417	}
	418	else
	419	{
	420	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	421	FPGA_REG3_ENET_GROUP8);
	422	}
	423	}
	424	}
	425	else
	426	{
	427	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	428	{
	429	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) \|
	430	FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
	431	}
	432	else
	433	{
	434	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) \|
	435	FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
	436	}
	437	}
	438	out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 \|
	439	FPGA_REG4_GPHY_MODE100 \| FPGA_REG4_GPHY_MODE1000 \|
	440	FPGA_REG4_GPHY_FRC_DPLX \| FPGA_REG4_CONNECT_PHYS);
	441
	442	/* reset the gigabyte phy if necessary */
	443	if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
	444	{
	445	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
	446	{
	447	out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
	448	udelay(10000);
	449	out8(FPGA_REG3, in8(FPGA_REG3) \| FPGA_REG3_GIGABIT_RESET_DISABLE);
	450	}
	451	else
	452	{
	453	out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
	454	udelay(10000);
	455	out8(FPGA_REG2, in8(FPGA_REG2) \| FPGA_REG2_GIGABIT_RESET_DISABLE);
	456	}
	457	}
	458
57275b69 SR	459	/*
	460	* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
	461	*/
	462	if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
	463	out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
	464	udelay(10000);
	465	out8(FPGA_REG2, in8(FPGA_REG2) \| FPGA_REG2_SMII_RESET_DISABLE);
	466	}
	467
0e6d798c WD	468	/* Turn off the LED's */
	469	out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) \|
	470	FPGA_REG3_STAT_LED8_DISAB \| FPGA_REG3_STAT_LED4_DISAB \|
	471	FPGA_REG3_STAT_LED2_DISAB \| FPGA_REG3_STAT_LED1_DISAB);
	472
	473	return;
	474	}
	475
	476	#ifdef CONFIG_POST
	477	/*
	478	* Returns 1 if keys pressed to start the power-on long-running tests
	479	* Called from board_init_f().
	480	*/
	481	int post_hotkeys_pressed(void)
	482	{
	483
	484	return (ctrlc());
	485	}
	486	#endif