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0e6d798c WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* Board specific FPGA stuff ... */ | |
6d0f6bcf | 25 | #define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00) |
0e6d798c WD |
26 | #define FPGA_REG0_SSCG_MASK 0x80 |
27 | #define FPGA_REG0_SSCG_DISABLE 0x00 | |
28 | #define FPGA_REG0_SSCG_ENABLE 0x80 | |
29 | #define FPGA_REG0_BOOT_MASK 0x40 | |
30 | #define FPGA_REG0_BOOT_LARGE_FLASH 0x00 | |
31 | #define FPGA_REG0_BOOT_SMALL_FLASH 0x40 | |
32 | #define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */ | |
33 | #define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */ | |
34 | #define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */ | |
35 | #define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */ | |
36 | #define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */ | |
37 | #define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */ | |
38 | #define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */ | |
39 | #define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */ | |
40 | #define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */ | |
41 | #define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */ | |
42 | #define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */ | |
43 | #define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */ | |
44 | #define FPGA_REG0_ARBITER_MASK 0x04 | |
45 | #define FPGA_REG0_ARBITER_EXT 0x00 | |
46 | #define FPGA_REG0_ARBITER_INT 0x04 | |
47 | #define FPGA_REG0_ONBOARD_FLASH_MASK 0x02 | |
48 | #define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00 | |
49 | #define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02 | |
50 | #define FPGA_REG0_FLASH 0x01 | |
6d0f6bcf | 51 | #define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01) |
0e6d798c WD |
52 | #define FPGA_REG1_9772_FSELFBX_MASK 0x80 |
53 | #define FPGA_REG1_9772_FSELFBX_6 0x00 | |
54 | #define FPGA_REG1_9772_FSELFBX_10 0x80 | |
55 | #define FPGA_REG1_9531_SX_MASK 0x60 | |
56 | #define FPGA_REG1_9531_SX_33MHZ 0x00 | |
57 | #define FPGA_REG1_9531_SX_100MHZ 0x20 | |
58 | #define FPGA_REG1_9531_SX_66MHZ 0x40 | |
59 | #define FPGA_REG1_9531_SX_133MHZ 0x60 | |
60 | #define FPGA_REG1_9772_FSELBX_MASK 0x18 | |
61 | #define FPGA_REG1_9772_FSELBX_4 0x00 | |
62 | #define FPGA_REG1_9772_FSELBX_6 0x08 | |
63 | #define FPGA_REG1_9772_FSELBX_8 0x10 | |
64 | #define FPGA_REG1_9772_FSELBX_10 0x18 | |
65 | #define FPGA_REG1_SOURCE_MASK 0x07 | |
66 | #define FPGA_REG1_SOURCE_TC 0x00 | |
67 | #define FPGA_REG1_SOURCE_66MHZ 0x01 | |
68 | #define FPGA_REG1_SOURCE_50MHZ 0x02 | |
69 | #define FPGA_REG1_SOURCE_33MHZ 0x03 | |
70 | #define FPGA_REG1_SOURCE_25MHZ 0x04 | |
71 | #define FPGA_REG1_SOURCE_SSDIV1 0x05 | |
72 | #define FPGA_REG1_SOURCE_SSDIV2 0x06 | |
73 | #define FPGA_REG1_SOURCE_SSDIV4 0x07 | |
6d0f6bcf | 74 | #define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02) |
0e6d798c WD |
75 | #define FPGA_REG2_TC0 0x80 |
76 | #define FPGA_REG2_TC1 0x40 | |
77 | #define FPGA_REG2_TC2 0x20 | |
78 | #define FPGA_REG2_TC3 0x10 | |
79 | #define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/ | |
80 | #define FPGA_REG2_EXT_INTFACE_MASK 0x04 | |
81 | #define FPGA_REG2_EXT_INTFACE_ENABLE 0x00 | |
82 | #define FPGA_REG2_EXT_INTFACE_DISABLE 0x04 | |
57275b69 | 83 | #define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/ |
0e6d798c | 84 | #define FPGA_REG2_DEFAULT_UART1_N 0x01 |
6d0f6bcf | 85 | #define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03) |
0e6d798c WD |
86 | #define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/ |
87 | #define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/ | |
88 | #define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/ | |
89 | #define FPGA_REG3_ENET_GROUP0 0x00 | |
90 | #define FPGA_REG3_ENET_GROUP1 0x10 | |
91 | #define FPGA_REG3_ENET_GROUP2 0x20 | |
92 | #define FPGA_REG3_ENET_GROUP3 0x30 | |
93 | #define FPGA_REG3_ENET_GROUP4 0x40 | |
94 | #define FPGA_REG3_ENET_GROUP5 0x50 | |
95 | #define FPGA_REG3_ENET_GROUP6 0x60 | |
96 | #define FPGA_REG3_ENET_GROUP7 0x70 | |
97 | #define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/ | |
98 | #define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/ | |
99 | #define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/ | |
100 | #define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/ | |
101 | #define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/ | |
102 | #define FPGA_REG3_STAT_MASK 0x0F | |
103 | #define FPGA_REG3_STAT_LED8_ENAB 0x08 | |
104 | #define FPGA_REG3_STAT_LED4_ENAB 0x04 | |
105 | #define FPGA_REG3_STAT_LED2_ENAB 0x02 | |
106 | #define FPGA_REG3_STAT_LED1_ENAB 0x01 | |
107 | #define FPGA_REG3_STAT_LED8_DISAB 0x00 | |
108 | #define FPGA_REG3_STAT_LED4_DISAB 0x00 | |
109 | #define FPGA_REG3_STAT_LED2_DISAB 0x00 | |
110 | #define FPGA_REG3_STAT_LED1_DISAB 0x00 | |
6d0f6bcf | 111 | #define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04) |
0e6d798c WD |
112 | #define FPGA_REG4_GPHY_MODE10 0x80 |
113 | #define FPGA_REG4_GPHY_MODE100 0x40 | |
114 | #define FPGA_REG4_GPHY_MODE1000 0x20 | |
115 | #define FPGA_REG4_GPHY_FRC_DPLX 0x10 | |
116 | #define FPGA_REG4_GPHY_ANEG_DIS 0x08 | |
117 | #define FPGA_REG4_CONNECT_PHYS 0x04 | |
118 | ||
119 | ||
120 | #define SDR0_CUST0_ENET3_MASK 0x00000080 | |
121 | #define SDR0_CUST0_ENET3_COPPER 0x00000000 | |
122 | #define SDR0_CUST0_ENET3_FIBER 0x00000080 | |
123 | #define SDR0_CUST0_RGMII3_MASK 0x00000070 | |
124 | #define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4) | |
125 | #define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07) | |
126 | #define SDR0_CUST0_RGMII3_DISAB 0x00000000 | |
127 | #define SDR0_CUST0_RGMII3_RTBI 0x00000040 | |
128 | #define SDR0_CUST0_RGMII3_RGMII 0x00000050 | |
129 | #define SDR0_CUST0_RGMII3_TBI 0x00000060 | |
130 | #define SDR0_CUST0_RGMII3_GMII 0x00000070 | |
131 | #define SDR0_CUST0_ENET2_MASK 0x00000008 | |
132 | #define SDR0_CUST0_ENET2_COPPER 0x00000000 | |
133 | #define SDR0_CUST0_ENET2_FIBER 0x00000008 | |
134 | #define SDR0_CUST0_RGMII2_MASK 0x00000007 | |
135 | #define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) | |
136 | #define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07) | |
137 | #define SDR0_CUST0_RGMII2_DISAB 0x00000000 | |
138 | #define SDR0_CUST0_RGMII2_RTBI 0x00000004 | |
139 | #define SDR0_CUST0_RGMII2_RGMII 0x00000005 | |
140 | #define SDR0_CUST0_RGMII2_TBI 0x00000006 | |
141 | #define SDR0_CUST0_RGMII2_GMII 0x00000007 |