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887e2ec9 SR |
1 | /* |
2 | * | |
3 | * See file CREDITS for list of people who contributed to this | |
4 | * project. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of | |
9 | * the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
19 | * MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <ppc_asm.tmpl> | |
c68f59fe | 23 | #include <asm-ppc/mmu.h> |
887e2ec9 SR |
24 | #include <config.h> |
25 | ||
887e2ec9 SR |
26 | /************************************************************************** |
27 | * TLB TABLE | |
28 | * | |
29 | * This table is used by the cpu boot code to setup the initial tlb | |
30 | * entries. Rather than make broad assumptions in the cpu source tree, | |
31 | * this table lets each board set things up however they like. | |
32 | * | |
33 | * Pointer to the table is returned in r1 | |
34 | * | |
35 | *************************************************************************/ | |
36 | .section .bootpg,"ax" | |
37 | .globl tlbtab | |
38 | ||
39 | tlbtab: | |
40 | tlbtab_start | |
41 | ||
4d332dbe NG |
42 | /* vxWorks needs this as first entry for the Machine Check interrupt */ |
43 | tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
887e2ec9 SR |
44 | |
45 | /* TLB-entry for DDR SDRAM (Up to 2GB) */ | |
ea2e1428 SR |
46 | #ifdef CONFIG_4xx_DCACHE |
47 | tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) | |
48 | #else | |
887e2ec9 | 49 | tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) |
ea2e1428 | 50 | #endif |
887e2ec9 | 51 | |
4d332dbe NG |
52 | /* TLB-entry for EBC */ |
53 | tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
54 | ||
55 | /* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the | |
56 | * speed up boot process. It is patched after relocation to enable SA_I | |
57 | */ | |
58 | #ifndef CONFIG_NAND_SPL | |
59 | tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G ) | |
60 | #else | |
61 | tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) | |
62 | #endif | |
63 | ||
887e2ec9 SR |
64 | #ifdef CFG_INIT_RAM_DCACHE |
65 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ | |
66 | tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) | |
67 | #endif | |
68 | ||
69 | /* TLB-entry for PCI Memory */ | |
70 | tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I ) | |
71 | tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I ) | |
72 | tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I ) | |
73 | tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I ) | |
74 | ||
887e2ec9 SR |
75 | /* TLB-entry for NAND */ |
76 | tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
77 | ||
78 | /* TLB-entry for Internal Registers & OCM */ | |
79 | tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I ) | |
80 | ||
81 | /*TLB-entry PCI registers*/ | |
82 | tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) | |
83 | ||
84 | /* TLB-entry for peripherals */ | |
85 | tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
86 | ||
81b73dec GJ |
87 | /* TLB-entry PCI IO Space - from sr@denx.de */ |
88 | tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) | |
89 | ||
887e2ec9 SR |
90 | tlbtab_end |
91 | ||
92 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
93 | /* | |
94 | * For NAND booting the first TLB has to be reconfigured to full size | |
95 | * and with caching disabled after running from RAM! | |
96 | */ | |
97 | #define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M) | |
98 | #define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1) | |
99 | #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) | |
100 | ||
101 | .globl reconfig_tlb0 | |
102 | reconfig_tlb0: | |
103 | sync | |
104 | isync | |
105 | addi r4,r0,0x0000 /* TLB entry #0 */ | |
106 | lis r5,TLB00@h | |
107 | ori r5,r5,TLB00@l | |
108 | tlbwe r5,r4,0x0000 /* Save it out */ | |
109 | lis r5,TLB01@h | |
110 | ori r5,r5,TLB01@l | |
111 | tlbwe r5,r4,0x0001 /* Save it out */ | |
112 | lis r5,TLB02@h | |
113 | ori r5,r5,TLB02@l | |
114 | tlbwe r5,r4,0x0002 /* Save it out */ | |
115 | sync | |
116 | isync | |
117 | blr | |
118 | #endif |