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Commit | Line | Data |
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887e2ec9 | 1 | /* |
5132106a | 2 | * (C) Copyright 2006-2009 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
865f0f97 | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 SR |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
13628884 SR |
26 | #include <libfdt.h> |
27 | #include <fdt_support.h> | |
4fb25a3d | 28 | #include <ppc4xx.h> |
b05e8bf5 | 29 | #include <asm/gpio.h> |
887e2ec9 | 30 | #include <asm/processor.h> |
5a5958b7 | 31 | #include <asm/io.h> |
83a49c8d | 32 | #include <asm/bitops.h> |
887e2ec9 SR |
33 | |
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
d873133f | 36 | #if !defined(CONFIG_SYS_NO_FLASH) |
6d0f6bcf | 37 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
d873133f | 38 | #endif |
887e2ec9 | 39 | |
5132106a SR |
40 | extern void __ft_board_setup(void *blob, bd_t *bd); |
41 | ulong flash_get_size(ulong base, int banknum); | |
1b3c360c | 42 | |
23c51a2d SR |
43 | static inline u32 get_async_pci_freq(void) |
44 | { | |
45 | if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & | |
46 | CONFIG_SYS_BCSR5_PCI66EN) | |
47 | return 66666666; | |
48 | else | |
49 | return 33333333; | |
50 | } | |
51 | ||
887e2ec9 SR |
52 | int board_early_init_f(void) |
53 | { | |
a78bc443 SR |
54 | u32 sdr0_cust0; |
55 | u32 sdr0_pfc1, sdr0_pfc2; | |
56 | u32 reg; | |
887e2ec9 | 57 | |
d1c3b275 SR |
58 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
59 | mtdcr(EBC0_CFGDATA, 0xb8400000); | |
887e2ec9 | 60 | |
83a49c8d | 61 | /* |
887e2ec9 | 62 | * Setup the interrupt controller polarities, triggers, etc. |
83a49c8d | 63 | */ |
952e7760 SR |
64 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
65 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
66 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
67 | mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ | |
68 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
69 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
70 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 71 | |
952e7760 SR |
72 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
73 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
74 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
75 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ | |
76 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ | |
77 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
78 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 79 | |
952e7760 SR |
80 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
81 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
82 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
83 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
84 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
85 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
86 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 87 | |
23c51a2d SR |
88 | /* Check and reconfigure the PCI sync clock if necessary */ |
89 | ppc4xx_pci_sync_clock_config(get_async_pci_freq()); | |
90 | ||
887e2ec9 | 91 | /* 50MHz tmrclk */ |
6d0f6bcf | 92 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); |
887e2ec9 SR |
93 | |
94 | /* clear write protects */ | |
6d0f6bcf | 95 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); |
887e2ec9 SR |
96 | |
97 | /* enable Ethernet */ | |
6d0f6bcf | 98 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); |
887e2ec9 SR |
99 | |
100 | /* enable USB device */ | |
6d0f6bcf | 101 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); |
887e2ec9 | 102 | |
b738654d | 103 | /* select Ethernet (and optionally IIC1) pins */ |
887e2ec9 | 104 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
83a49c8d MF |
105 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
106 | SDR0_PFC1_SELECT_CONFIG_4; | |
b738654d MN |
107 | #ifdef CONFIG_I2C_MULTI_BUS |
108 | sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); | |
109 | #endif | |
eab10073 SF |
110 | /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ |
111 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; | |
112 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; | |
113 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; | |
114 | ||
887e2ec9 | 115 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
83a49c8d MF |
116 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
117 | SDR0_PFC2_SELECT_CONFIG_4; | |
887e2ec9 SR |
118 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
119 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
120 | ||
121 | /* PCI arbiter enabled */ | |
d1c3b275 SR |
122 | mfsdr(SDR0_PCI0, reg); |
123 | mtsdr(SDR0_PCI0, 0x80000000 | reg); | |
887e2ec9 SR |
124 | |
125 | /* setup NAND FLASH */ | |
126 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 127 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
128 | SDR0_CUST0_NDFC_ENABLE | |
129 | SDR0_CUST0_NDFC_BW_8_BIT | | |
130 | SDR0_CUST0_NDFC_ARE_MASK | | |
6d0f6bcf | 131 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
511d0c72 | 132 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
133 | |
134 | return 0; | |
135 | } | |
136 | ||
887e2ec9 SR |
137 | int misc_init_r(void) |
138 | { | |
d873133f | 139 | #if !defined(CONFIG_SYS_NO_FLASH) |
887e2ec9 SR |
140 | uint pbcr; |
141 | int size_val = 0; | |
d873133f | 142 | #endif |
854bc8da | 143 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
144 | unsigned long usb2d0cr = 0; |
145 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
146 | unsigned long sdr0_pfc1; | |
147 | char *act = getenv("usbact"); | |
854bc8da | 148 | #endif |
d873133f | 149 | u32 reg; |
887e2ec9 | 150 | |
d873133f | 151 | #if !defined(CONFIG_SYS_NO_FLASH) |
83a49c8d | 152 | /* Re-do flash sizing to get full correct info */ |
1b3c360c SR |
153 | |
154 | /* adjust flash start and offset */ | |
155 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
156 | gd->bd->bi_flashoffset = 0; | |
157 | ||
887e2ec9 | 158 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
d1c3b275 | 159 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 160 | #else |
d1c3b275 | 161 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 162 | #endif |
d1c3b275 | 163 | pbcr = mfdcr(EBC0_CFGDATA); |
865f0f97 | 164 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
887e2ec9 SR |
165 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
166 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
d1c3b275 | 167 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 168 | #else |
d1c3b275 | 169 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 170 | #endif |
d1c3b275 | 171 | mtdcr(EBC0_CFGDATA, pbcr); |
887e2ec9 | 172 | |
1b3c360c SR |
173 | /* |
174 | * Re-check to get correct base address | |
175 | */ | |
176 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 | 177 | |
5a1aceb0 | 178 | #ifdef CONFIG_ENV_IS_IN_FLASH |
887e2ec9 SR |
179 | /* Monitor protection ON by default */ |
180 | (void)flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 181 | -CONFIG_SYS_MONITOR_LEN, |
887e2ec9 SR |
182 | 0xffffffff, |
183 | &flash_info[0]); | |
184 | ||
185 | /* Env protection ON by default */ | |
186 | (void)flash_protect(FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
187 | CONFIG_ENV_ADDR_REDUND, |
188 | CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, | |
887e2ec9 SR |
189 | &flash_info[0]); |
190 | #endif | |
d873133f | 191 | #endif /* CONFIG_SYS_NO_FLASH */ |
887e2ec9 SR |
192 | |
193 | /* | |
194 | * USB suff... | |
195 | */ | |
854bc8da | 196 | #ifdef CONFIG_440EPX |
83a49c8d | 197 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
887e2ec9 | 198 | /* SDR Setting */ |
511d0c72 | 199 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 200 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
201 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
202 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
203 | |
204 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 205 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 206 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 207 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 208 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 209 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 210 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 211 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 212 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 213 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 | 214 | |
83a49c8d MF |
215 | /* |
216 | * An 8-bit/60MHz interface is the only possible alternative | |
217 | * when connecting the Device to the PHY | |
218 | */ | |
511d0c72 | 219 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
83a49c8d | 220 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 221 | |
83a49c8d MF |
222 | /* |
223 | * To enable the USB 2.0 Device function | |
224 | * through the UTMI interface | |
225 | */ | |
511d0c72 | 226 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
83a49c8d | 227 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; |
887e2ec9 | 228 | |
511d0c72 | 229 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
83a49c8d | 230 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; |
887e2ec9 | 231 | |
511d0c72 | 232 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 233 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
234 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
235 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
236 | |
237 | /*clear resets*/ | |
238 | udelay (1000); | |
239 | mtsdr(SDR0_SRST1, 0x00000000); | |
240 | udelay (1000); | |
241 | mtsdr(SDR0_SRST0, 0x00000000); | |
242 | ||
243 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
244 | ||
245 | } else if (strcmp(act, "dev") == 0) { | |
246 | /*-------------------PATCH-------------------------------*/ | |
247 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
248 | ||
249 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 250 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
887e2ec9 | 251 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 252 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 253 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 254 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 255 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 256 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 SR |
257 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
258 | ||
259 | udelay (1000); | |
260 | mtsdr(SDR0_SRST1, 0x672c6000); | |
261 | ||
262 | udelay (1000); | |
263 | mtsdr(SDR0_SRST0, 0x00000080); | |
264 | ||
265 | udelay (1000); | |
266 | mtsdr(SDR0_SRST1, 0x60206000); | |
267 | ||
268 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
269 | ||
270 | udelay (1000); | |
271 | mtsdr(SDR0_SRST1, 0x60306000); | |
272 | /*-------------------PATCH-------------------------------*/ | |
273 | ||
274 | /* SDR Setting */ | |
511d0c72 | 275 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 | 276 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
f780b833 | 277 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
278 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
279 | ||
280 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 281 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 282 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 283 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; |
887e2ec9 | 284 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 285 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; |
887e2ec9 | 286 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 287 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; |
887e2ec9 | 288 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 289 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; |
887e2ec9 SR |
290 | |
291 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
83a49c8d | 292 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; |
887e2ec9 SR |
293 | |
294 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
83a49c8d | 295 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; |
887e2ec9 SR |
296 | |
297 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
83a49c8d | 298 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; |
887e2ec9 | 299 | |
511d0c72 WD |
300 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
301 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
f780b833 | 302 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
303 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
304 | ||
83a49c8d | 305 | /* clear resets */ |
887e2ec9 SR |
306 | udelay (1000); |
307 | mtsdr(SDR0_SRST1, 0x00000000); | |
308 | udelay (1000); | |
309 | mtsdr(SDR0_SRST0, 0x00000000); | |
310 | ||
311 | printf("USB: Device(int phy)\n"); | |
312 | } | |
854bc8da | 313 | #endif /* CONFIG_440EPX */ |
887e2ec9 | 314 | |
8ce16f55 JO |
315 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
316 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); | |
317 | mtsdr(SDR0_SRST1, reg); | |
318 | ||
a78bc443 SR |
319 | /* |
320 | * Clear PLB4A0_ACR[WRP] | |
321 | * This fix will make the MAL burst disabling patch for the Linux | |
322 | * EMAC driver obsolete. | |
323 | */ | |
d1c3b275 SR |
324 | reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; |
325 | mtdcr(PLB4_ACR, reg); | |
a78bc443 | 326 | |
887e2ec9 SR |
327 | return 0; |
328 | } | |
329 | ||
330 | int checkboard(void) | |
331 | { | |
332 | char *s = getenv("serial#"); | |
e0b9ea8c | 333 | u8 rev; |
23c51a2d | 334 | u32 clock = get_async_pci_freq(); |
887e2ec9 | 335 | |
854bc8da | 336 | #ifdef CONFIG_440EPX |
887e2ec9 | 337 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
338 | #else |
339 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
340 | #endif | |
e0b9ea8c | 341 | |
6d0f6bcf | 342 | rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); |
23c51a2d | 343 | printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); |
e0b9ea8c | 344 | |
887e2ec9 SR |
345 | if (s != NULL) { |
346 | puts(", serial# "); | |
347 | puts(s); | |
348 | } | |
349 | putc('\n'); | |
350 | ||
23c51a2d SR |
351 | /* |
352 | * Reconfiguration of the PCI sync clock is already done, | |
353 | * now check again if everything is in range: | |
354 | */ | |
355 | if (ppc4xx_pci_sync_clock_config(clock)) { | |
356 | printf("ERROR: PCI clocking incorrect (async=%d " | |
357 | "sync=%ld)!\n", clock, get_PCI_freq()); | |
358 | } | |
359 | ||
887e2ec9 SR |
360 | return (0); |
361 | } | |
362 | ||
1f84021a MF |
363 | #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) |
364 | /* | |
365 | * Assign interrupts to PCI devices. | |
366 | */ | |
367 | void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) | |
368 | { | |
d1631fe1 | 369 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); |
1f84021a MF |
370 | } |
371 | #endif | |
372 | ||
83a49c8d MF |
373 | /* |
374 | * pci_pre_init | |
887e2ec9 | 375 | * |
83a49c8d MF |
376 | * This routine is called just prior to registering the hose and gives |
377 | * the board the opportunity to check things. Returning a value of zero | |
378 | * indicates that things are bad & PCI initialization should be aborted. | |
887e2ec9 | 379 | * |
83a49c8d MF |
380 | * Different boards may wish to customize the pci controller structure |
381 | * (add regions, override default access routines, etc) or perform | |
382 | * certain pre-initialization actions. | |
383 | */ | |
466fff1a | 384 | #if defined(CONFIG_PCI) |
887e2ec9 SR |
385 | int pci_pre_init(struct pci_controller *hose) |
386 | { | |
387 | unsigned long addr; | |
887e2ec9 | 388 | |
83a49c8d MF |
389 | /* |
390 | * Set priority for all PLB3 devices to 0. | |
391 | * Set PLB3 arbiter to fair mode. | |
392 | */ | |
d1c3b275 SR |
393 | mfsdr(SD0_AMP1, addr); |
394 | mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); | |
395 | addr = mfdcr(PLB3_ACR); | |
396 | mtdcr(PLB3_ACR, addr | 0x80000000); | |
887e2ec9 | 397 | |
83a49c8d MF |
398 | /* |
399 | * Set priority for all PLB4 devices to 0. | |
400 | */ | |
d1c3b275 SR |
401 | mfsdr(SD0_AMP0, addr); |
402 | mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); | |
403 | addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ | |
404 | mtdcr(PLB4_ACR, addr); | |
887e2ec9 | 405 | |
83a49c8d MF |
406 | /* |
407 | * Set Nebula PLB4 arbiter to fair mode. | |
408 | */ | |
887e2ec9 | 409 | /* Segment0 */ |
d1c3b275 SR |
410 | addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; |
411 | addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; | |
412 | addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; | |
413 | addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; | |
414 | mtdcr(PLB0_ACR, addr); | |
887e2ec9 SR |
415 | |
416 | /* Segment1 */ | |
d1c3b275 SR |
417 | addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; |
418 | addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; | |
419 | addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; | |
420 | addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; | |
421 | mtdcr(PLB1_ACR, addr); | |
887e2ec9 | 422 | |
1f84021a MF |
423 | #ifdef CONFIG_PCI_PNP |
424 | hose->fixup_irq = sequoia_pci_fixup_irq; | |
425 | #endif | |
887e2ec9 SR |
426 | return 1; |
427 | } | |
466fff1a | 428 | #endif /* defined(CONFIG_PCI) */ |
887e2ec9 | 429 | |
6d0f6bcf | 430 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) |
887e2ec9 SR |
431 | void pci_master_init(struct pci_controller *hose) |
432 | { | |
433 | unsigned short temp_short; | |
434 | ||
83a49c8d MF |
435 | /* |
436 | * Write the PowerPC440 EP PCI Configuration regs. | |
437 | * Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
438 | * Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
439 | */ | |
887e2ec9 SR |
440 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
441 | pci_write_config_word(0, PCI_COMMAND, | |
442 | temp_short | PCI_COMMAND_MASTER | | |
443 | PCI_COMMAND_MEMORY); | |
444 | } | |
6d0f6bcf | 445 | #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ |
887e2ec9 | 446 | |
a11e0696 IL |
447 | #if defined(CONFIG_POST) |
448 | /* | |
449 | * Returns 1 if keys pressed to start the power-on long-running tests | |
450 | * Called from board_init_f(). | |
451 | */ | |
452 | int post_hotkeys_pressed(void) | |
453 | { | |
454 | return 0; /* No hotkeys supported */ | |
455 | } | |
456 | #endif /* CONFIG_POST */ | |
5132106a | 457 | |
d873133f | 458 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) |
5132106a SR |
459 | /* |
460 | * On NAND-booting sequoia, we need to patch the chips select numbers | |
461 | * in the dtb (CS0 - NAND, CS3 - NOR) | |
462 | */ | |
463 | void ft_board_setup(void *blob, bd_t *bd) | |
464 | { | |
465 | int rc; | |
466 | int len; | |
467 | int nodeoffset; | |
468 | struct fdt_property *prop; | |
469 | u32 *reg; | |
470 | char path[32]; | |
471 | ||
472 | /* First do common fdt setup */ | |
473 | __ft_board_setup(blob, bd); | |
474 | ||
475 | /* And now configure NOR chip select to 3 instead of 0 */ | |
476 | strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); | |
477 | nodeoffset = fdt_path_offset(blob, path); | |
478 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
479 | if (prop == NULL) { | |
480 | printf("Unable to update NOR chip select for NAND booting\n"); | |
481 | return; | |
482 | } | |
483 | reg = (u32 *)&prop->data[0]; | |
484 | reg[0] = 3; | |
485 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
486 | if (rc) { | |
487 | printf("Unable to update property NOR mappings, err=%s\n", | |
488 | fdt_strerror(rc)); | |
489 | return; | |
490 | } | |
491 | ||
492 | /* And now configure NAND chip select to 0 instead of 3 */ | |
493 | strcpy(path, "/plb/opb/ebc/ndfc@3,0"); | |
494 | nodeoffset = fdt_path_offset(blob, path); | |
495 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
496 | if (prop == NULL) { | |
497 | printf("Unable to update NDFC chip select for NAND booting\n"); | |
498 | return; | |
499 | } | |
500 | reg = (u32 *)&prop->data[0]; | |
501 | reg[0] = 0; | |
502 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
503 | if (rc) { | |
504 | printf("Unable to update property NDFC mappings, err=%s\n", | |
505 | fdt_strerror(rc)); | |
506 | return; | |
507 | } | |
508 | } | |
509 | #endif /* CONFIG_NAND_U_BOOT */ |