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Commit | Line | Data |
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887e2ec9 SR |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
511d0c72 | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 SR |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <asm/processor.h> | |
27 | #include <ppc440.h> | |
28 | #include "sequoia.h" | |
29 | ||
30 | DECLARE_GLOBAL_DATA_PTR; | |
31 | ||
32 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
33 | ||
1b3c360c SR |
34 | ulong flash_get_size (ulong base, int banknum); |
35 | ||
887e2ec9 SR |
36 | int board_early_init_f(void) |
37 | { | |
38 | unsigned long sdr0_cust0; | |
39 | unsigned long sdr0_pfc1, sdr0_pfc2; | |
40 | register uint reg; | |
41 | ||
42 | mtdcr(ebccfga, xbcfg); | |
43 | mtdcr(ebccfgd, 0xb8400000); | |
44 | ||
45 | /*-------------------------------------------------------------------- | |
46 | * Setup the GPIO pins | |
47 | *-------------------------------------------------------------------*/ | |
48 | /* test-only: take GPIO init from pcs440ep ???? in config file */ | |
49 | out32(GPIO0_OR, 0x00000000); | |
50 | out32(GPIO0_TCR, 0x0000000f); | |
51 | out32(GPIO0_OSRL, 0x50015400); | |
52 | out32(GPIO0_OSRH, 0x550050aa); | |
53 | out32(GPIO0_TSRL, 0x50015400); | |
54 | out32(GPIO0_TSRH, 0x55005000); | |
55 | out32(GPIO0_ISR1L, 0x50000000); | |
56 | out32(GPIO0_ISR1H, 0x00000000); | |
57 | out32(GPIO0_ISR2L, 0x00000000); | |
58 | out32(GPIO0_ISR2H, 0x00000100); | |
59 | out32(GPIO0_ISR3L, 0x00000000); | |
60 | out32(GPIO0_ISR3H, 0x00000000); | |
61 | ||
62 | out32(GPIO1_OR, 0x00000000); | |
63 | out32(GPIO1_TCR, 0xc2000000); | |
64 | out32(GPIO1_OSRL, 0x5c280000); | |
65 | out32(GPIO1_OSRH, 0x00000000); | |
66 | out32(GPIO1_TSRL, 0x0c000000); | |
67 | out32(GPIO1_TSRH, 0x00000000); | |
68 | out32(GPIO1_ISR1L, 0x00005550); | |
69 | out32(GPIO1_ISR1H, 0x00000000); | |
70 | out32(GPIO1_ISR2L, 0x00050000); | |
71 | out32(GPIO1_ISR2H, 0x00000000); | |
72 | out32(GPIO1_ISR3L, 0x01400000); | |
73 | out32(GPIO1_ISR3H, 0x00000000); | |
74 | ||
75 | /*-------------------------------------------------------------------- | |
76 | * Setup the interrupt controller polarities, triggers, etc. | |
77 | *-------------------------------------------------------------------*/ | |
78 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
79 | mtdcr(uic0er, 0x00000000); /* disable all */ | |
80 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ | |
81 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ | |
82 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ | |
83 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ | |
84 | mtdcr(uic0sr, 0xffffffff); /* clear all */ | |
85 | ||
86 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
87 | mtdcr(uic1er, 0x00000000); /* disable all */ | |
88 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ | |
89 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ | |
90 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ | |
91 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ | |
92 | mtdcr(uic1sr, 0xffffffff); /* clear all */ | |
93 | ||
94 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
95 | mtdcr(uic2er, 0x00000000); /* disable all */ | |
96 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ | |
97 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ | |
98 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ | |
99 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ | |
100 | mtdcr(uic2sr, 0xffffffff); /* clear all */ | |
101 | ||
102 | /* 50MHz tmrclk */ | |
103 | *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00; | |
104 | ||
105 | /* clear write protects */ | |
106 | *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00; | |
107 | ||
108 | /* enable Ethernet */ | |
109 | *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00; | |
110 | ||
111 | /* enable USB device */ | |
112 | *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20; | |
113 | ||
114 | /* select Ethernet pins */ | |
115 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
116 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4; | |
117 | mfsdr(SDR0_PFC2, sdr0_pfc2); | |
118 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4; | |
119 | mtsdr(SDR0_PFC2, sdr0_pfc2); | |
120 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
121 | ||
122 | /* PCI arbiter enabled */ | |
123 | mfsdr(sdr_pci0, reg); | |
124 | mtsdr(sdr_pci0, 0x80000000 | reg); | |
125 | ||
126 | /* setup NAND FLASH */ | |
127 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 128 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
129 | SDR0_CUST0_NDFC_ENABLE | |
130 | SDR0_CUST0_NDFC_BW_8_BIT | | |
131 | SDR0_CUST0_NDFC_ARE_MASK | | |
132 | (0x80000000 >> (28 + CFG_NAND_CS)); | |
511d0c72 | 133 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
134 | |
135 | return 0; | |
136 | } | |
137 | ||
138 | /*---------------------------------------------------------------------------+ | |
139 | | misc_init_r. | |
140 | +---------------------------------------------------------------------------*/ | |
141 | int misc_init_r(void) | |
142 | { | |
143 | uint pbcr; | |
144 | int size_val = 0; | |
854bc8da | 145 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
146 | unsigned long usb2d0cr = 0; |
147 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
148 | unsigned long sdr0_pfc1; | |
149 | char *act = getenv("usbact"); | |
854bc8da | 150 | #endif |
887e2ec9 SR |
151 | |
152 | /* | |
153 | * FLASH stuff... | |
154 | */ | |
155 | ||
156 | /* Re-do sizing to get full correct info */ | |
1b3c360c SR |
157 | |
158 | /* adjust flash start and offset */ | |
159 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
160 | gd->bd->bi_flashoffset = 0; | |
161 | ||
887e2ec9 SR |
162 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
163 | mtdcr(ebccfga, pb3cr); | |
164 | #else | |
165 | mtdcr(ebccfga, pb0cr); | |
166 | #endif | |
167 | pbcr = mfdcr(ebccfgd); | |
168 | switch (gd->bd->bi_flashsize) { | |
169 | case 1 << 20: | |
170 | size_val = 0; | |
171 | break; | |
172 | case 2 << 20: | |
173 | size_val = 1; | |
174 | break; | |
175 | case 4 << 20: | |
176 | size_val = 2; | |
177 | break; | |
178 | case 8 << 20: | |
179 | size_val = 3; | |
180 | break; | |
181 | case 16 << 20: | |
182 | size_val = 4; | |
183 | break; | |
184 | case 32 << 20: | |
185 | size_val = 5; | |
186 | break; | |
187 | case 64 << 20: | |
188 | size_val = 6; | |
189 | break; | |
190 | case 128 << 20: | |
191 | size_val = 7; | |
192 | break; | |
193 | } | |
194 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); | |
195 | #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) | |
196 | mtdcr(ebccfga, pb3cr); | |
197 | #else | |
198 | mtdcr(ebccfga, pb0cr); | |
199 | #endif | |
200 | mtdcr(ebccfgd, pbcr); | |
201 | ||
1b3c360c SR |
202 | /* |
203 | * Re-check to get correct base address | |
204 | */ | |
205 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 SR |
206 | |
207 | #ifdef CFG_ENV_IS_IN_FLASH | |
208 | /* Monitor protection ON by default */ | |
209 | (void)flash_protect(FLAG_PROTECT_SET, | |
210 | -CFG_MONITOR_LEN, | |
211 | 0xffffffff, | |
212 | &flash_info[0]); | |
213 | ||
214 | /* Env protection ON by default */ | |
215 | (void)flash_protect(FLAG_PROTECT_SET, | |
216 | CFG_ENV_ADDR_REDUND, | |
217 | CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, | |
218 | &flash_info[0]); | |
219 | #endif | |
220 | ||
221 | /* | |
222 | * USB suff... | |
223 | */ | |
854bc8da | 224 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
225 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
226 | /* SDR Setting */ | |
511d0c72 WD |
227 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
228 | mfsdr(SDR0_USB0, usb2d0cr); | |
229 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
230 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
231 | |
232 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
233 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
511d0c72 WD |
234 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
235 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ | |
887e2ec9 | 236 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
511d0c72 | 237 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
887e2ec9 | 238 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 239 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
887e2ec9 | 240 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 241 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
887e2ec9 SR |
242 | |
243 | /* An 8-bit/60MHz interface is the only possible alternative | |
244 | when connecting the Device to the PHY */ | |
511d0c72 WD |
245 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
246 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ | |
887e2ec9 | 247 | |
511d0c72 WD |
248 | /* To enable the USB 2.0 Device function through the UTMI interface */ |
249 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
250 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/ | |
887e2ec9 | 251 | |
511d0c72 WD |
252 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
253 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ | |
887e2ec9 | 254 | |
511d0c72 WD |
255 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
256 | mtsdr(SDR0_USB0, usb2d0cr); | |
257 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
258 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
259 | |
260 | /*clear resets*/ | |
261 | udelay (1000); | |
262 | mtsdr(SDR0_SRST1, 0x00000000); | |
263 | udelay (1000); | |
264 | mtsdr(SDR0_SRST0, 0x00000000); | |
265 | ||
266 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
267 | ||
268 | } else if (strcmp(act, "dev") == 0) { | |
269 | /*-------------------PATCH-------------------------------*/ | |
270 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
271 | ||
272 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
273 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
274 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
511d0c72 | 275 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ |
887e2ec9 | 276 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 277 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ |
887e2ec9 | 278 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 279 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ |
887e2ec9 SR |
280 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
281 | ||
282 | udelay (1000); | |
283 | mtsdr(SDR0_SRST1, 0x672c6000); | |
284 | ||
285 | udelay (1000); | |
286 | mtsdr(SDR0_SRST0, 0x00000080); | |
287 | ||
288 | udelay (1000); | |
289 | mtsdr(SDR0_SRST1, 0x60206000); | |
290 | ||
291 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
292 | ||
293 | udelay (1000); | |
294 | mtsdr(SDR0_SRST1, 0x60306000); | |
295 | /*-------------------PATCH-------------------------------*/ | |
296 | ||
297 | /* SDR Setting */ | |
511d0c72 | 298 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 SR |
299 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
300 | mfsdr(SDR0_USB0, usb2d0cr); | |
301 | mfsdr(SDR0_PFC1, sdr0_pfc1); | |
302 | ||
303 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
304 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ | |
511d0c72 | 305 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
887e2ec9 SR |
306 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/ |
307 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; | |
511d0c72 | 308 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/ |
887e2ec9 | 309 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
511d0c72 | 310 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/ |
887e2ec9 | 311 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
511d0c72 | 312 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/ |
887e2ec9 SR |
313 | |
314 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
511d0c72 | 315 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/ |
887e2ec9 SR |
316 | |
317 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
511d0c72 | 318 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/ |
887e2ec9 SR |
319 | |
320 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
511d0c72 | 321 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/ |
887e2ec9 | 322 | |
511d0c72 WD |
323 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
324 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
887e2ec9 SR |
325 | mtsdr(SDR0_USB0, usb2d0cr); |
326 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
327 | ||
328 | /*clear resets*/ | |
329 | udelay (1000); | |
330 | mtsdr(SDR0_SRST1, 0x00000000); | |
331 | udelay (1000); | |
332 | mtsdr(SDR0_SRST0, 0x00000000); | |
333 | ||
334 | printf("USB: Device(int phy)\n"); | |
335 | } | |
854bc8da | 336 | #endif /* CONFIG_440EPX */ |
887e2ec9 SR |
337 | |
338 | return 0; | |
339 | } | |
340 | ||
341 | int checkboard(void) | |
342 | { | |
343 | char *s = getenv("serial#"); | |
344 | ||
854bc8da | 345 | #ifdef CONFIG_440EPX |
887e2ec9 | 346 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
347 | #else |
348 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
349 | #endif | |
887e2ec9 SR |
350 | if (s != NULL) { |
351 | puts(", serial# "); | |
352 | puts(s); | |
353 | } | |
354 | putc('\n'); | |
355 | ||
356 | return (0); | |
357 | } | |
358 | ||
359 | #if defined(CFG_DRAM_TEST) | |
360 | int testdram(void) | |
361 | { | |
362 | unsigned long *mem = (unsigned long *)0; | |
363 | const unsigned long kend = (1024 / sizeof(unsigned long)); | |
364 | unsigned long k, n; | |
365 | ||
366 | mtmsr(0); | |
367 | ||
368 | for (k = 0; k < CFG_MBYTES_SDRAM; | |
369 | ++k, mem += (1024 / sizeof(unsigned long))) { | |
370 | if ((k & 1023) == 0) { | |
371 | printf("%3d MB\r", k / 1024); | |
372 | } | |
373 | ||
374 | memset(mem, 0xaaaaaaaa, 1024); | |
375 | for (n = 0; n < kend; ++n) { | |
376 | if (mem[n] != 0xaaaaaaaa) { | |
377 | printf("SDRAM test fails at: %08x\n", | |
378 | (uint) & mem[n]); | |
379 | return 1; | |
380 | } | |
381 | } | |
382 | ||
383 | memset(mem, 0x55555555, 1024); | |
384 | for (n = 0; n < kend; ++n) { | |
385 | if (mem[n] != 0x55555555) { | |
386 | printf("SDRAM test fails at: %08x\n", | |
387 | (uint) & mem[n]); | |
388 | return 1; | |
389 | } | |
390 | } | |
391 | } | |
392 | printf("SDRAM test passes\n"); | |
393 | return 0; | |
394 | } | |
395 | #endif | |
396 | ||
397 | /************************************************************************* | |
398 | * pci_pre_init | |
399 | * | |
400 | * This routine is called just prior to registering the hose and gives | |
401 | * the board the opportunity to check things. Returning a value of zero | |
402 | * indicates that things are bad & PCI initialization should be aborted. | |
403 | * | |
404 | * Different boards may wish to customize the pci controller structure | |
405 | * (add regions, override default access routines, etc) or perform | |
406 | * certain pre-initialization actions. | |
407 | * | |
408 | ************************************************************************/ | |
409 | #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) | |
410 | int pci_pre_init(struct pci_controller *hose) | |
411 | { | |
412 | unsigned long addr; | |
413 | #if 0 | |
414 | /*--------------------------------------------------------------------------+ | |
415 | * Cactus is always configured as the host & requires the | |
416 | * PCI arbiter to be enabled ??? | |
417 | *--------------------------------------------------------------------------*/ | |
418 | unsigned long strap; | |
419 | mfsdr(sdr_sdstp1, strap); | |
420 | if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { | |
421 | printf("PCI: SDR0_STRP1[PAE] not set.\n"); | |
422 | printf("PCI: Configuration aborted.\n"); | |
423 | return 0; | |
424 | } | |
425 | #endif | |
426 | ||
427 | /*-------------------------------------------------------------------------+ | |
428 | | Set priority for all PLB3 devices to 0. | |
429 | | Set PLB3 arbiter to fair mode. | |
430 | +-------------------------------------------------------------------------*/ | |
431 | mfsdr(sdr_amp1, addr); | |
432 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); | |
433 | addr = mfdcr(plb3_acr); | |
434 | mtdcr(plb3_acr, addr | 0x80000000); | |
435 | ||
436 | /*-------------------------------------------------------------------------+ | |
437 | | Set priority for all PLB4 devices to 0. | |
438 | +-------------------------------------------------------------------------*/ | |
439 | mfsdr(sdr_amp0, addr); | |
440 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); | |
441 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ | |
442 | mtdcr(plb4_acr, addr); | |
443 | ||
444 | /*-------------------------------------------------------------------------+ | |
445 | | Set Nebula PLB4 arbiter to fair mode. | |
446 | +-------------------------------------------------------------------------*/ | |
447 | /* Segment0 */ | |
448 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; | |
449 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; | |
450 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; | |
451 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; | |
452 | mtdcr(plb0_acr, addr); | |
453 | ||
454 | /* Segment1 */ | |
455 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; | |
456 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; | |
457 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; | |
458 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; | |
459 | mtdcr(plb1_acr, addr); | |
460 | ||
461 | return 1; | |
462 | } | |
463 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ | |
464 | ||
465 | /************************************************************************* | |
466 | * pci_target_init | |
467 | * | |
468 | * The bootstrap configuration provides default settings for the pci | |
469 | * inbound map (PIM). But the bootstrap config choices are limited and | |
470 | * may not be sufficient for a given board. | |
471 | * | |
472 | ************************************************************************/ | |
473 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
474 | void pci_target_init(struct pci_controller *hose) | |
475 | { | |
476 | /*--------------------------------------------------------------------------+ | |
477 | * Set up Direct MMIO registers | |
478 | *--------------------------------------------------------------------------*/ | |
479 | /*--------------------------------------------------------------------------+ | |
480 | | PowerPC440EPX PCI Master configuration. | |
481 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. | |
482 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF | |
483 | | Use byte reversed out routines to handle endianess. | |
484 | | Make this region non-prefetchable. | |
485 | +--------------------------------------------------------------------------*/ | |
486 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
487 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ | |
488 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ | |
489 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
490 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
491 | ||
492 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ | |
493 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ | |
494 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ | |
495 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ | |
496 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ | |
497 | ||
498 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ | |
499 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ | |
500 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ | |
501 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ | |
502 | ||
503 | /*--------------------------------------------------------------------------+ | |
504 | * Set up Configuration registers | |
505 | *--------------------------------------------------------------------------*/ | |
506 | ||
507 | /* Program the board's subsystem id/vendor id */ | |
508 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, | |
509 | CFG_PCI_SUBSYS_VENDORID); | |
510 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); | |
511 | ||
512 | /* Configure command register as bus master */ | |
513 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); | |
514 | ||
515 | /* 240nS PCI clock */ | |
516 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); | |
517 | ||
518 | /* No error reporting */ | |
519 | pci_write_config_word(0, PCI_ERREN, 0); | |
520 | ||
521 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); | |
522 | ||
523 | } | |
524 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
525 | ||
526 | /************************************************************************* | |
527 | * pci_master_init | |
528 | * | |
529 | ************************************************************************/ | |
530 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) | |
531 | void pci_master_init(struct pci_controller *hose) | |
532 | { | |
533 | unsigned short temp_short; | |
534 | ||
535 | /*--------------------------------------------------------------------------+ | |
536 | | Write the PowerPC440 EP PCI Configuration regs. | |
537 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). | |
538 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). | |
539 | +--------------------------------------------------------------------------*/ | |
540 | pci_read_config_word(0, PCI_COMMAND, &temp_short); | |
541 | pci_write_config_word(0, PCI_COMMAND, | |
542 | temp_short | PCI_COMMAND_MASTER | | |
543 | PCI_COMMAND_MEMORY); | |
544 | } | |
545 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ | |
546 | ||
547 | /************************************************************************* | |
548 | * is_pci_host | |
549 | * | |
550 | * This routine is called to determine if a pci scan should be | |
551 | * performed. With various hardware environments (especially cPCI and | |
552 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
553 | * bit in the strap register, or generic host/adapter assumptions. | |
554 | * | |
555 | * Rather than hard-code a bad assumption in the general 440 code, the | |
556 | * 440 pci code requires the board to decide at runtime. | |
557 | * | |
558 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
559 | * | |
560 | * | |
561 | ************************************************************************/ | |
562 | #if defined(CONFIG_PCI) | |
563 | int is_pci_host(struct pci_controller *hose) | |
564 | { | |
565 | /* Cactus is always configured as host. */ | |
566 | return (1); | |
567 | } | |
568 | #endif /* defined(CONFIG_PCI) */ |