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Commit | Line | Data |
---|---|---|
887e2ec9 | 1 | /* |
5132106a | 2 | * (C) Copyright 2006-2009 |
887e2ec9 SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com | |
865f0f97 | 7 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
887e2ec9 | 8 | * |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
887e2ec9 SR |
10 | */ |
11 | ||
12 | #include <common.h> | |
e895a4b0 | 13 | #include <errno.h> |
13628884 SR |
14 | #include <libfdt.h> |
15 | #include <fdt_support.h> | |
b36df561 | 16 | #include <asm/ppc4xx.h> |
09887762 | 17 | #include <asm/ppc4xx-gpio.h> |
887e2ec9 | 18 | #include <asm/processor.h> |
5a5958b7 | 19 | #include <asm/io.h> |
83a49c8d | 20 | #include <asm/bitops.h> |
887e2ec9 SR |
21 | |
22 | DECLARE_GLOBAL_DATA_PTR; | |
23 | ||
d873133f | 24 | #if !defined(CONFIG_SYS_NO_FLASH) |
6d0f6bcf | 25 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
d873133f | 26 | #endif |
887e2ec9 | 27 | |
5132106a SR |
28 | extern void __ft_board_setup(void *blob, bd_t *bd); |
29 | ulong flash_get_size(ulong base, int banknum); | |
1b3c360c | 30 | |
23c51a2d SR |
31 | static inline u32 get_async_pci_freq(void) |
32 | { | |
33 | if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & | |
34 | CONFIG_SYS_BCSR5_PCI66EN) | |
35 | return 66666666; | |
36 | else | |
37 | return 33333333; | |
38 | } | |
39 | ||
887e2ec9 SR |
40 | int board_early_init_f(void) |
41 | { | |
a78bc443 SR |
42 | u32 sdr0_cust0; |
43 | u32 sdr0_pfc1, sdr0_pfc2; | |
44 | u32 reg; | |
887e2ec9 | 45 | |
d1c3b275 SR |
46 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
47 | mtdcr(EBC0_CFGDATA, 0xb8400000); | |
887e2ec9 | 48 | |
83a49c8d | 49 | /* |
887e2ec9 | 50 | * Setup the interrupt controller polarities, triggers, etc. |
83a49c8d | 51 | */ |
952e7760 SR |
52 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
53 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
54 | mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */ | |
55 | mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */ | |
56 | mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */ | |
57 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
58 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 59 | |
952e7760 SR |
60 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ |
61 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
62 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
63 | mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */ | |
64 | mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */ | |
65 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
66 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 67 | |
952e7760 SR |
68 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ |
69 | mtdcr(UIC2ER, 0x00000000); /* disable all */ | |
70 | mtdcr(UIC2CR, 0x00000000); /* all non-critical */ | |
71 | mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */ | |
72 | mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */ | |
73 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
74 | mtdcr(UIC2SR, 0xffffffff); /* clear all */ | |
887e2ec9 | 75 | |
23c51a2d SR |
76 | /* Check and reconfigure the PCI sync clock if necessary */ |
77 | ppc4xx_pci_sync_clock_config(get_async_pci_freq()); | |
78 | ||
887e2ec9 | 79 | /* 50MHz tmrclk */ |
6d0f6bcf | 80 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00); |
887e2ec9 SR |
81 | |
82 | /* clear write protects */ | |
6d0f6bcf | 83 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00); |
887e2ec9 SR |
84 | |
85 | /* enable Ethernet */ | |
6d0f6bcf | 86 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00); |
887e2ec9 SR |
87 | |
88 | /* enable USB device */ | |
6d0f6bcf | 89 | out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20); |
887e2ec9 | 90 | |
b738654d | 91 | /* select Ethernet (and optionally IIC1) pins */ |
887e2ec9 | 92 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
83a49c8d MF |
93 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
94 | SDR0_PFC1_SELECT_CONFIG_4; | |
b738654d MN |
95 | #ifdef CONFIG_I2C_MULTI_BUS |
96 | sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL); | |
97 | #endif | |
eab10073 SF |
98 | /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */ |
99 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS; | |
100 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS; | |
101 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS; | |
102 | ||
887e2ec9 | 103 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
83a49c8d MF |
104 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
105 | SDR0_PFC2_SELECT_CONFIG_4; | |
887e2ec9 SR |
106 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
107 | mtsdr(SDR0_PFC1, sdr0_pfc1); | |
108 | ||
109 | /* PCI arbiter enabled */ | |
d1c3b275 SR |
110 | mfsdr(SDR0_PCI0, reg); |
111 | mtsdr(SDR0_PCI0, 0x80000000 | reg); | |
887e2ec9 SR |
112 | |
113 | /* setup NAND FLASH */ | |
114 | mfsdr(SDR0_CUST0, sdr0_cust0); | |
511d0c72 | 115 | sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL | |
887e2ec9 SR |
116 | SDR0_CUST0_NDFC_ENABLE | |
117 | SDR0_CUST0_NDFC_BW_8_BIT | | |
118 | SDR0_CUST0_NDFC_ARE_MASK | | |
6d0f6bcf | 119 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
511d0c72 | 120 | mtsdr(SDR0_CUST0, sdr0_cust0); |
887e2ec9 SR |
121 | |
122 | return 0; | |
123 | } | |
124 | ||
887e2ec9 SR |
125 | int misc_init_r(void) |
126 | { | |
d873133f | 127 | #if !defined(CONFIG_SYS_NO_FLASH) |
887e2ec9 SR |
128 | uint pbcr; |
129 | int size_val = 0; | |
d873133f | 130 | #endif |
854bc8da | 131 | #ifdef CONFIG_440EPX |
887e2ec9 SR |
132 | unsigned long usb2d0cr = 0; |
133 | unsigned long usb2phy0cr, usb2h0cr = 0; | |
134 | unsigned long sdr0_pfc1; | |
135 | char *act = getenv("usbact"); | |
854bc8da | 136 | #endif |
d873133f | 137 | u32 reg; |
887e2ec9 | 138 | |
d873133f | 139 | #if !defined(CONFIG_SYS_NO_FLASH) |
83a49c8d | 140 | /* Re-do flash sizing to get full correct info */ |
1b3c360c SR |
141 | |
142 | /* adjust flash start and offset */ | |
143 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; | |
144 | gd->bd->bi_flashoffset = 0; | |
145 | ||
345b77ba | 146 | #if defined(CONFIG_SYS_RAMBOOT) |
d1c3b275 | 147 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 148 | #else |
d1c3b275 | 149 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 150 | #endif |
d1c3b275 | 151 | pbcr = mfdcr(EBC0_CFGDATA); |
865f0f97 | 152 | size_val = ffs(gd->bd->bi_flashsize) - 21; |
887e2ec9 | 153 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
345b77ba | 154 | #if defined(CONFIG_SYS_RAMBOOT) |
d1c3b275 | 155 | mtdcr(EBC0_CFGADDR, PB3CR); |
887e2ec9 | 156 | #else |
d1c3b275 | 157 | mtdcr(EBC0_CFGADDR, PB0CR); |
887e2ec9 | 158 | #endif |
d1c3b275 | 159 | mtdcr(EBC0_CFGDATA, pbcr); |
887e2ec9 | 160 | |
1b3c360c SR |
161 | /* |
162 | * Re-check to get correct base address | |
163 | */ | |
164 | flash_get_size(gd->bd->bi_flashstart, 0); | |
887e2ec9 | 165 | |
5a1aceb0 | 166 | #ifdef CONFIG_ENV_IS_IN_FLASH |
887e2ec9 SR |
167 | /* Monitor protection ON by default */ |
168 | (void)flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 169 | -CONFIG_SYS_MONITOR_LEN, |
887e2ec9 SR |
170 | 0xffffffff, |
171 | &flash_info[0]); | |
172 | ||
173 | /* Env protection ON by default */ | |
174 | (void)flash_protect(FLAG_PROTECT_SET, | |
0e8d1586 JCPV |
175 | CONFIG_ENV_ADDR_REDUND, |
176 | CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, | |
887e2ec9 SR |
177 | &flash_info[0]); |
178 | #endif | |
d873133f | 179 | #endif /* CONFIG_SYS_NO_FLASH */ |
887e2ec9 SR |
180 | |
181 | /* | |
182 | * USB suff... | |
183 | */ | |
854bc8da | 184 | #ifdef CONFIG_440EPX |
83a49c8d | 185 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
887e2ec9 | 186 | /* SDR Setting */ |
511d0c72 | 187 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 188 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
189 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
190 | mfsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
191 | |
192 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 193 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 194 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 195 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 196 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 197 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 198 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 199 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 200 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 201 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 | 202 | |
83a49c8d MF |
203 | /* |
204 | * An 8-bit/60MHz interface is the only possible alternative | |
205 | * when connecting the Device to the PHY | |
206 | */ | |
511d0c72 | 207 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; |
83a49c8d | 208 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; |
887e2ec9 | 209 | |
83a49c8d MF |
210 | /* |
211 | * To enable the USB 2.0 Device function | |
212 | * through the UTMI interface | |
213 | */ | |
511d0c72 | 214 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
83a49c8d | 215 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; |
887e2ec9 | 216 | |
511d0c72 | 217 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; |
83a49c8d | 218 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; |
887e2ec9 | 219 | |
511d0c72 | 220 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
f780b833 | 221 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
511d0c72 WD |
222 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
223 | mtsdr(SDR0_USB2H0CR, usb2h0cr); | |
887e2ec9 SR |
224 | |
225 | /*clear resets*/ | |
226 | udelay (1000); | |
227 | mtsdr(SDR0_SRST1, 0x00000000); | |
228 | udelay (1000); | |
229 | mtsdr(SDR0_SRST0, 0x00000000); | |
230 | ||
231 | printf("USB: Host(int phy) Device(ext phy)\n"); | |
232 | ||
233 | } else if (strcmp(act, "dev") == 0) { | |
234 | /*-------------------PATCH-------------------------------*/ | |
235 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
236 | ||
237 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 238 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
887e2ec9 | 239 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 240 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; |
887e2ec9 | 241 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 242 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; |
887e2ec9 | 243 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 244 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; |
887e2ec9 SR |
245 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
246 | ||
247 | udelay (1000); | |
248 | mtsdr(SDR0_SRST1, 0x672c6000); | |
249 | ||
250 | udelay (1000); | |
251 | mtsdr(SDR0_SRST0, 0x00000080); | |
252 | ||
253 | udelay (1000); | |
254 | mtsdr(SDR0_SRST1, 0x60206000); | |
255 | ||
256 | *(unsigned int *)(0xe0000350) = 0x00000001; | |
257 | ||
258 | udelay (1000); | |
259 | mtsdr(SDR0_SRST1, 0x60306000); | |
260 | /*-------------------PATCH-------------------------------*/ | |
261 | ||
262 | /* SDR Setting */ | |
511d0c72 | 263 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
887e2ec9 | 264 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
f780b833 | 265 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
266 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
267 | ||
268 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; | |
83a49c8d | 269 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; |
511d0c72 | 270 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; |
83a49c8d | 271 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; |
887e2ec9 | 272 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; |
83a49c8d | 273 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; |
887e2ec9 | 274 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; |
83a49c8d | 275 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; |
887e2ec9 | 276 | usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; |
83a49c8d | 277 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; |
887e2ec9 SR |
278 | |
279 | usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; | |
83a49c8d | 280 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; |
887e2ec9 SR |
281 | |
282 | usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; | |
83a49c8d | 283 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; |
887e2ec9 SR |
284 | |
285 | sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK; | |
83a49c8d | 286 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; |
887e2ec9 | 287 | |
511d0c72 WD |
288 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
289 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); | |
f780b833 | 290 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
887e2ec9 SR |
291 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
292 | ||
83a49c8d | 293 | /* clear resets */ |
887e2ec9 SR |
294 | udelay (1000); |
295 | mtsdr(SDR0_SRST1, 0x00000000); | |
296 | udelay (1000); | |
297 | mtsdr(SDR0_SRST0, 0x00000000); | |
298 | ||
299 | printf("USB: Device(int phy)\n"); | |
300 | } | |
854bc8da | 301 | #endif /* CONFIG_440EPX */ |
887e2ec9 | 302 | |
8ce16f55 JO |
303 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
304 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); | |
305 | mtsdr(SDR0_SRST1, reg); | |
306 | ||
a78bc443 SR |
307 | /* |
308 | * Clear PLB4A0_ACR[WRP] | |
309 | * This fix will make the MAL burst disabling patch for the Linux | |
310 | * EMAC driver obsolete. | |
311 | */ | |
5e7abce9 SR |
312 | reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; |
313 | mtdcr(PLB4A0_ACR, reg); | |
a78bc443 | 314 | |
887e2ec9 SR |
315 | return 0; |
316 | } | |
317 | ||
318 | int checkboard(void) | |
319 | { | |
f0c0b3a9 WD |
320 | char buf[64]; |
321 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
e0b9ea8c | 322 | u8 rev; |
23c51a2d | 323 | u32 clock = get_async_pci_freq(); |
887e2ec9 | 324 | |
854bc8da | 325 | #ifdef CONFIG_440EPX |
887e2ec9 | 326 | printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board"); |
854bc8da SR |
327 | #else |
328 | printf("Board: Rainier - AMCC PPC440GRx Evaluation Board"); | |
329 | #endif | |
e0b9ea8c | 330 | |
6d0f6bcf | 331 | rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)); |
23c51a2d | 332 | printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000); |
e0b9ea8c | 333 | |
f0c0b3a9 | 334 | if (i > 0) { |
887e2ec9 | 335 | puts(", serial# "); |
f0c0b3a9 | 336 | puts(buf); |
887e2ec9 SR |
337 | } |
338 | putc('\n'); | |
339 | ||
23c51a2d SR |
340 | /* |
341 | * Reconfiguration of the PCI sync clock is already done, | |
342 | * now check again if everything is in range: | |
343 | */ | |
344 | if (ppc4xx_pci_sync_clock_config(clock)) { | |
345 | printf("ERROR: PCI clocking incorrect (async=%d " | |
346 | "sync=%ld)!\n", clock, get_PCI_freq()); | |
347 | } | |
348 | ||
887e2ec9 SR |
349 | return (0); |
350 | } | |
351 | ||
1f84021a MF |
352 | #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP) |
353 | /* | |
354 | * Assign interrupts to PCI devices. | |
355 | */ | |
a760b020 | 356 | void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
1f84021a | 357 | { |
d1631fe1 | 358 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2); |
1f84021a MF |
359 | } |
360 | #endif | |
361 | ||
345b77ba | 362 | #if defined(CONFIG_SYS_RAMBOOT) |
5132106a SR |
363 | /* |
364 | * On NAND-booting sequoia, we need to patch the chips select numbers | |
365 | * in the dtb (CS0 - NAND, CS3 - NOR) | |
366 | */ | |
e895a4b0 | 367 | int ft_board_setup(void *blob, bd_t *bd) |
5132106a SR |
368 | { |
369 | int rc; | |
370 | int len; | |
371 | int nodeoffset; | |
372 | struct fdt_property *prop; | |
373 | u32 *reg; | |
374 | char path[32]; | |
375 | ||
376 | /* First do common fdt setup */ | |
377 | __ft_board_setup(blob, bd); | |
378 | ||
379 | /* And now configure NOR chip select to 3 instead of 0 */ | |
380 | strcpy(path, "/plb/opb/ebc/nor_flash@0,0"); | |
381 | nodeoffset = fdt_path_offset(blob, path); | |
382 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
383 | if (prop == NULL) { | |
384 | printf("Unable to update NOR chip select for NAND booting\n"); | |
e895a4b0 | 385 | return -FDT_ERR_NOTFOUND; |
5132106a SR |
386 | } |
387 | reg = (u32 *)&prop->data[0]; | |
388 | reg[0] = 3; | |
389 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
390 | if (rc) { | |
e895a4b0 SG |
391 | printf("Unable to update property NOR mappings\n"); |
392 | return rc; | |
5132106a SR |
393 | } |
394 | ||
395 | /* And now configure NAND chip select to 0 instead of 3 */ | |
396 | strcpy(path, "/plb/opb/ebc/ndfc@3,0"); | |
397 | nodeoffset = fdt_path_offset(blob, path); | |
398 | prop = fdt_get_property_w(blob, nodeoffset, "reg", &len); | |
399 | if (prop == NULL) { | |
400 | printf("Unable to update NDFC chip select for NAND booting\n"); | |
e895a4b0 | 401 | return len; |
5132106a SR |
402 | } |
403 | reg = (u32 *)&prop->data[0]; | |
404 | reg[0] = 0; | |
405 | rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1); | |
406 | if (rc) { | |
e895a4b0 SG |
407 | printf("Unable to update property NDFC mapping\n"); |
408 | return rc; | |
5132106a | 409 | } |
e895a4b0 SG |
410 | |
411 | return 0; | |
5132106a | 412 | } |
345b77ba | 413 | #endif /* CONFIG_SYS_RAMBOOT */ |