]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/amcc/sequoia/sequoia.c
Fix incorrect use of getenv() before relocation
[people/ms/u-boot.git] / board / amcc / sequoia / sequoia.c
CommitLineData
887e2ec9 1/*
5132106a 2 * (C) Copyright 2006-2009
887e2ec9
SR
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2006
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
865f0f97 7 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
887e2ec9
SR
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
13628884
SR
26#include <libfdt.h>
27#include <fdt_support.h>
b36df561 28#include <asm/ppc4xx.h>
09887762 29#include <asm/ppc4xx-gpio.h>
887e2ec9 30#include <asm/processor.h>
5a5958b7 31#include <asm/io.h>
83a49c8d 32#include <asm/bitops.h>
887e2ec9
SR
33
34DECLARE_GLOBAL_DATA_PTR;
35
d873133f 36#if !defined(CONFIG_SYS_NO_FLASH)
6d0f6bcf 37extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
d873133f 38#endif
887e2ec9 39
5132106a
SR
40extern void __ft_board_setup(void *blob, bd_t *bd);
41ulong flash_get_size(ulong base, int banknum);
1b3c360c 42
23c51a2d
SR
43static inline u32 get_async_pci_freq(void)
44{
45 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
46 CONFIG_SYS_BCSR5_PCI66EN)
47 return 66666666;
48 else
49 return 33333333;
50}
51
887e2ec9
SR
52int board_early_init_f(void)
53{
a78bc443
SR
54 u32 sdr0_cust0;
55 u32 sdr0_pfc1, sdr0_pfc2;
56 u32 reg;
887e2ec9 57
d1c3b275
SR
58 mtdcr(EBC0_CFGADDR, EBC0_CFG);
59 mtdcr(EBC0_CFGDATA, 0xb8400000);
887e2ec9 60
83a49c8d 61 /*
887e2ec9 62 * Setup the interrupt controller polarities, triggers, etc.
83a49c8d 63 */
952e7760
SR
64 mtdcr(UIC0SR, 0xffffffff); /* clear all */
65 mtdcr(UIC0ER, 0x00000000); /* disable all */
66 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
67 mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
68 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
69 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
70 mtdcr(UIC0SR, 0xffffffff); /* clear all */
887e2ec9 71
952e7760
SR
72 mtdcr(UIC1SR, 0xffffffff); /* clear all */
73 mtdcr(UIC1ER, 0x00000000); /* disable all */
74 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
75 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
76 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
77 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
78 mtdcr(UIC1SR, 0xffffffff); /* clear all */
887e2ec9 79
952e7760
SR
80 mtdcr(UIC2SR, 0xffffffff); /* clear all */
81 mtdcr(UIC2ER, 0x00000000); /* disable all */
82 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
83 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
84 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
85 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
86 mtdcr(UIC2SR, 0xffffffff); /* clear all */
887e2ec9 87
23c51a2d
SR
88 /* Check and reconfigure the PCI sync clock if necessary */
89 ppc4xx_pci_sync_clock_config(get_async_pci_freq());
90
887e2ec9 91 /* 50MHz tmrclk */
6d0f6bcf 92 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
887e2ec9
SR
93
94 /* clear write protects */
6d0f6bcf 95 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
887e2ec9
SR
96
97 /* enable Ethernet */
6d0f6bcf 98 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
887e2ec9
SR
99
100 /* enable USB device */
6d0f6bcf 101 out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
887e2ec9 102
b738654d 103 /* select Ethernet (and optionally IIC1) pins */
887e2ec9 104 mfsdr(SDR0_PFC1, sdr0_pfc1);
83a49c8d
MF
105 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
106 SDR0_PFC1_SELECT_CONFIG_4;
b738654d
MN
107#ifdef CONFIG_I2C_MULTI_BUS
108 sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
109#endif
eab10073
SF
110 /* Two UARTs, so we need 4-pin mode. Also, we want CTS/RTS mode. */
111 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
112 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
113 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
114
887e2ec9 115 mfsdr(SDR0_PFC2, sdr0_pfc2);
83a49c8d
MF
116 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
117 SDR0_PFC2_SELECT_CONFIG_4;
887e2ec9
SR
118 mtsdr(SDR0_PFC2, sdr0_pfc2);
119 mtsdr(SDR0_PFC1, sdr0_pfc1);
120
121 /* PCI arbiter enabled */
d1c3b275
SR
122 mfsdr(SDR0_PCI0, reg);
123 mtsdr(SDR0_PCI0, 0x80000000 | reg);
887e2ec9
SR
124
125 /* setup NAND FLASH */
126 mfsdr(SDR0_CUST0, sdr0_cust0);
511d0c72 127 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
887e2ec9
SR
128 SDR0_CUST0_NDFC_ENABLE |
129 SDR0_CUST0_NDFC_BW_8_BIT |
130 SDR0_CUST0_NDFC_ARE_MASK |
6d0f6bcf 131 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
511d0c72 132 mtsdr(SDR0_CUST0, sdr0_cust0);
887e2ec9
SR
133
134 return 0;
135}
136
887e2ec9
SR
137int misc_init_r(void)
138{
d873133f 139#if !defined(CONFIG_SYS_NO_FLASH)
887e2ec9
SR
140 uint pbcr;
141 int size_val = 0;
d873133f 142#endif
854bc8da 143#ifdef CONFIG_440EPX
887e2ec9
SR
144 unsigned long usb2d0cr = 0;
145 unsigned long usb2phy0cr, usb2h0cr = 0;
146 unsigned long sdr0_pfc1;
147 char *act = getenv("usbact");
854bc8da 148#endif
d873133f 149 u32 reg;
887e2ec9 150
d873133f 151#if !defined(CONFIG_SYS_NO_FLASH)
83a49c8d 152 /* Re-do flash sizing to get full correct info */
1b3c360c
SR
153
154 /* adjust flash start and offset */
155 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
156 gd->bd->bi_flashoffset = 0;
157
4adcbdc6
SR
158#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
159 defined(CONFIG_SYS_RAMBOOT)
d1c3b275 160 mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9 161#else
d1c3b275 162 mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9 163#endif
d1c3b275 164 pbcr = mfdcr(EBC0_CFGDATA);
865f0f97 165 size_val = ffs(gd->bd->bi_flashsize) - 21;
887e2ec9 166 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
4adcbdc6
SR
167#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \
168 defined(CONFIG_SYS_RAMBOOT)
d1c3b275 169 mtdcr(EBC0_CFGADDR, PB3CR);
887e2ec9 170#else
d1c3b275 171 mtdcr(EBC0_CFGADDR, PB0CR);
887e2ec9 172#endif
d1c3b275 173 mtdcr(EBC0_CFGDATA, pbcr);
887e2ec9 174
1b3c360c
SR
175 /*
176 * Re-check to get correct base address
177 */
178 flash_get_size(gd->bd->bi_flashstart, 0);
887e2ec9 179
5a1aceb0 180#ifdef CONFIG_ENV_IS_IN_FLASH
887e2ec9
SR
181 /* Monitor protection ON by default */
182 (void)flash_protect(FLAG_PROTECT_SET,
6d0f6bcf 183 -CONFIG_SYS_MONITOR_LEN,
887e2ec9
SR
184 0xffffffff,
185 &flash_info[0]);
186
187 /* Env protection ON by default */
188 (void)flash_protect(FLAG_PROTECT_SET,
0e8d1586
JCPV
189 CONFIG_ENV_ADDR_REDUND,
190 CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
887e2ec9
SR
191 &flash_info[0]);
192#endif
d873133f 193#endif /* CONFIG_SYS_NO_FLASH */
887e2ec9
SR
194
195 /*
196 * USB suff...
197 */
854bc8da 198#ifdef CONFIG_440EPX
83a49c8d 199 if (act == NULL || strcmp(act, "hostdev") == 0) {
887e2ec9 200 /* SDR Setting */
511d0c72 201 mfsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 202 mfsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
203 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
204 mfsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
205
206 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 207 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 208 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 209 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
887e2ec9 210 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 211 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 212 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 213 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 214 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 215 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9 216
83a49c8d
MF
217 /*
218 * An 8-bit/60MHz interface is the only possible alternative
219 * when connecting the Device to the PHY
220 */
511d0c72 221 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 222 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
887e2ec9 223
83a49c8d
MF
224 /*
225 * To enable the USB 2.0 Device function
226 * through the UTMI interface
227 */
511d0c72 228 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 229 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
887e2ec9 230
511d0c72 231 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 232 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
887e2ec9 233
511d0c72 234 mtsdr(SDR0_PFC1, sdr0_pfc1);
f780b833 235 mtsdr(SDR0_USB2D0CR, usb2d0cr);
511d0c72
WD
236 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
237 mtsdr(SDR0_USB2H0CR, usb2h0cr);
887e2ec9
SR
238
239 /*clear resets*/
240 udelay (1000);
241 mtsdr(SDR0_SRST1, 0x00000000);
242 udelay (1000);
243 mtsdr(SDR0_SRST0, 0x00000000);
244
245 printf("USB: Host(int phy) Device(ext phy)\n");
246
247 } else if (strcmp(act, "dev") == 0) {
248 /*-------------------PATCH-------------------------------*/
249 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
250
251 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 252 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
887e2ec9 253 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 254 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
887e2ec9 255 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 256 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
887e2ec9 257 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 258 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
887e2ec9
SR
259 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
260
261 udelay (1000);
262 mtsdr(SDR0_SRST1, 0x672c6000);
263
264 udelay (1000);
265 mtsdr(SDR0_SRST0, 0x00000080);
266
267 udelay (1000);
268 mtsdr(SDR0_SRST1, 0x60206000);
269
270 *(unsigned int *)(0xe0000350) = 0x00000001;
271
272 udelay (1000);
273 mtsdr(SDR0_SRST1, 0x60306000);
274 /*-------------------PATCH-------------------------------*/
275
276 /* SDR Setting */
511d0c72 277 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
887e2ec9 278 mfsdr(SDR0_USB2H0CR, usb2h0cr);
f780b833 279 mfsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
280 mfsdr(SDR0_PFC1, sdr0_pfc1);
281
282 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
83a49c8d 283 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
511d0c72 284 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
83a49c8d 285 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
887e2ec9 286 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
83a49c8d 287 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
887e2ec9 288 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
83a49c8d 289 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
887e2ec9 290 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
83a49c8d 291 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
887e2ec9
SR
292
293 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
83a49c8d 294 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
887e2ec9
SR
295
296 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
83a49c8d 297 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
887e2ec9
SR
298
299 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
83a49c8d 300 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
887e2ec9 301
511d0c72
WD
302 mtsdr(SDR0_USB2H0CR, usb2h0cr);
303 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
f780b833 304 mtsdr(SDR0_USB2D0CR, usb2d0cr);
887e2ec9
SR
305 mtsdr(SDR0_PFC1, sdr0_pfc1);
306
83a49c8d 307 /* clear resets */
887e2ec9
SR
308 udelay (1000);
309 mtsdr(SDR0_SRST1, 0x00000000);
310 udelay (1000);
311 mtsdr(SDR0_SRST0, 0x00000000);
312
313 printf("USB: Device(int phy)\n");
314 }
854bc8da 315#endif /* CONFIG_440EPX */
887e2ec9 316
8ce16f55
JO
317 mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
318 reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
319 mtsdr(SDR0_SRST1, reg);
320
a78bc443
SR
321 /*
322 * Clear PLB4A0_ACR[WRP]
323 * This fix will make the MAL burst disabling patch for the Linux
324 * EMAC driver obsolete.
325 */
5e7abce9
SR
326 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
327 mtdcr(PLB4A0_ACR, reg);
a78bc443 328
887e2ec9
SR
329 return 0;
330}
331
332int checkboard(void)
333{
f0c0b3a9
WD
334 char buf[64];
335 int i = getenv_f("serial#", buf, sizeof(buf));
e0b9ea8c 336 u8 rev;
23c51a2d 337 u32 clock = get_async_pci_freq();
887e2ec9 338
854bc8da 339#ifdef CONFIG_440EPX
887e2ec9 340 printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
854bc8da
SR
341#else
342 printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
343#endif
e0b9ea8c 344
6d0f6bcf 345 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
23c51a2d 346 printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
e0b9ea8c 347
f0c0b3a9 348 if (i > 0) {
887e2ec9 349 puts(", serial# ");
f0c0b3a9 350 puts(buf);
887e2ec9
SR
351 }
352 putc('\n');
353
23c51a2d
SR
354 /*
355 * Reconfiguration of the PCI sync clock is already done,
356 * now check again if everything is in range:
357 */
358 if (ppc4xx_pci_sync_clock_config(clock)) {
359 printf("ERROR: PCI clocking incorrect (async=%d "
360 "sync=%ld)!\n", clock, get_PCI_freq());
361 }
362
887e2ec9
SR
363 return (0);
364}
365
1f84021a
MF
366#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
367/*
368 * Assign interrupts to PCI devices.
369 */
a760b020 370void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
1f84021a 371{
d1631fe1 372 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
1f84021a
MF
373}
374#endif
375
d873133f 376#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
5132106a
SR
377/*
378 * On NAND-booting sequoia, we need to patch the chips select numbers
379 * in the dtb (CS0 - NAND, CS3 - NOR)
380 */
381void ft_board_setup(void *blob, bd_t *bd)
382{
383 int rc;
384 int len;
385 int nodeoffset;
386 struct fdt_property *prop;
387 u32 *reg;
388 char path[32];
389
390 /* First do common fdt setup */
391 __ft_board_setup(blob, bd);
392
393 /* And now configure NOR chip select to 3 instead of 0 */
394 strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
395 nodeoffset = fdt_path_offset(blob, path);
396 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
397 if (prop == NULL) {
398 printf("Unable to update NOR chip select for NAND booting\n");
399 return;
400 }
401 reg = (u32 *)&prop->data[0];
402 reg[0] = 3;
403 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
404 if (rc) {
405 printf("Unable to update property NOR mappings, err=%s\n",
406 fdt_strerror(rc));
407 return;
408 }
409
410 /* And now configure NAND chip select to 0 instead of 3 */
411 strcpy(path, "/plb/opb/ebc/ndfc@3,0");
412 nodeoffset = fdt_path_offset(blob, path);
413 prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
414 if (prop == NULL) {
415 printf("Unable to update NDFC chip select for NAND booting\n");
416 return;
417 }
418 reg = (u32 *)&prop->data[0];
419 reg[0] = 0;
420 rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
421 if (rc) {
422 printf("Unable to update property NDFC mappings, err=%s\n",
423 fdt_strerror(rc));
424 return;
425 }
426}
427#endif /* CONFIG_NAND_U_BOOT */