[people/ms/u-boot.git] / board / amcc / taishan / taishan.c

/*
 *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
 *
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>

#ifdef CFG_INIT_SHOW_RESET_REG
void show_reset_reg(void);
#endif

DECLARE_GLOBAL_DATA_PTR;

int lcd_init(void);

int board_early_init_f (void)
{
	unsigned long reg;
	volatile unsigned int *GpioOdr;
	volatile unsigned int *GpioTcr;
	volatile unsigned int *GpioOr;

	/*-------------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------------*/
	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*-------------------------------------------------------------------------+
	  | 64MB FLASH. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | LCM. Initialize bank 2 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | TMP. Initialize bank 3 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | Connector 4~7. Initialize bank 3~ 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb4ap,0);
	mtebc(pb4cr,0);
	mtebc(pb5ap,0);
	mtebc(pb5cr,0);
	mtebc(pb6ap,0);
	mtebc(pb6cr,0);
	mtebc(pb7ap,0);
	mtebc(pb7cr,0);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr (uic0sr, 0xffffffff);	/* clear all */
	mtdcr (uic0er, 0x00000000);	/* disable all */
	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic0sr, 0xffffffff);	/* clear all */

	mtdcr (uic1sr, 0xffffffff);	/* clear all */
	mtdcr (uic1er, 0x00000000);	/* disable all */
	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic1sr, 0xffffffff);	/* clear all */

	mtdcr (uic2sr, 0xffffffff);	/* clear all */
	mtdcr (uic2er, 0x00000000);	/* disable all */
	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic2sr, 0xffffffff);	/* clear all */

	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
	mtdcr (uicb0er, 0x00000000);	/* disable all */
	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
	mtdcr (uicb0pr, 0xfc000000);	/* */
	mtdcr (uicb0tr, 0x00000000);	/* */
	mtdcr (uicb0vr, 0x00000001);	/* */

	/* Enable two GPIO 10~11 and TraceA signal */
	mfsdr(sdr_pfc0,reg);
	reg |= 0x00300000;
	mtsdr(sdr_pfc0,reg);

	mfsdr(sdr_pfc1,reg);
	reg |= 0x00100000;
	mtsdr(sdr_pfc1,reg);

	/* Set GPIO 10 and 11 as output */
	GpioOdr	= (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
	GpioOr  = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);

	*GpioOdr &= ~(0x00300000);
	*GpioTcr |= 0x00300000;
	*GpioOr  |= 0x00300000;

	return 0;
}

int misc_init_r(void)
{
	lcd_init();

	return 0;
}

int checkboard (void)
{
	char *s = getenv ("serial#");

	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	if (s != NULL) {
		puts (", serial# ");
		puts (s);
	}
	putc ('\n');

#ifdef CFG_INIT_SHOW_RESET_REG
	show_reset_reg();
#endif

	return (0);
}

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 *	The ocotea board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(sdr_sdstp1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	return 1;
}
#endif /* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	 * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
	out32r( PCIX0_PIM0LAH, 0 );
	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );

	out32r( PCIX0_BAR0, 0 );

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );

	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* The ocotea board is always configured as host. */
	return(1);
}
#endif /* defined(CONFIG_PCI) */

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return (ctrlc());
}
#endif
Commit	Line	Data
5fb692ca SR	1	/*
	2	* Copyright (C) 2004 PaulReynolds@lhsolutions.com
	3	*
	4	* (C) Copyright 2007
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <spd_sdram.h>
	29	#include <ppc4xx_enet.h>
	30
	31	#ifdef CFG_INIT_SHOW_RESET_REG
	32	void show_reset_reg(void);
	33	#endif
	34
1218abf1 WD	35	DECLARE_GLOBAL_DATA_PTR;
1218abf1 WD	36
5fb692ca SR	37	int lcd_init(void);
	38
	39	int board_early_init_f (void)
	40	{
	41	unsigned long reg;
	42	volatile unsigned int *GpioOdr;
	43	volatile unsigned int *GpioTcr;
	44	volatile unsigned int *GpioOr;
	45
	46	/*-------------------------------------------------------------------------+
	47	\| Initialize EBC CONFIG
	48	+-------------------------------------------------------------------------*/
	49	mtebc(xbcfg, EBC_CFG_LE_UNLOCK \|
	50	EBC_CFG_PTD_ENABLE \| EBC_CFG_RTC_64PERCLK \|
	51	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	52	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_DEFAULT \|
	53	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
	54
	55	/*-------------------------------------------------------------------------+
	56	\| 64MB FLASH. Initialize bank 0 with default values.
	57	+-------------------------------------------------------------------------*/
	58	mtebc(pb0ap, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(15) \|
	59	EBC_BXAP_BCE_DISABLE \|
	60	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
	61	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
	62	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
	63	EBC_BXAP_BEM_WRITEONLY \|
	64	EBC_BXAP_PEN_DISABLED);
	65	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) \|
	66	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_32BIT);
	67
	68	/*-------------------------------------------------------------------------+
	69	\| FPGA. Initialize bank 1 with default values.
	70	+-------------------------------------------------------------------------*/
	71	mtebc(pb1ap, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(5) \|
	72	EBC_BXAP_BCE_DISABLE \|
	73	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
	74	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
	75	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
	76	EBC_BXAP_BEM_WRITEONLY \|
	77	EBC_BXAP_PEN_DISABLED);
	78	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) \|
	79	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	80
	81	/*-------------------------------------------------------------------------+
	82	\| LCM. Initialize bank 2 with default values.
	83	+-------------------------------------------------------------------------*/
	84	mtebc(pb2ap, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(64) \|
	85	EBC_BXAP_BCE_DISABLE \|
	86	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
	87	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
	88	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
	89	EBC_BXAP_BEM_WRITEONLY \|
	90	EBC_BXAP_PEN_DISABLED);
	91	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) \|
	92	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
	93
	94	/*-------------------------------------------------------------------------+
	95	\| TMP. Initialize bank 3 with default values.
	96	+-------------------------------------------------------------------------*/
	97	mtebc(pb3ap, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(128) \|
	98	EBC_BXAP_BCE_DISABLE \|
	99	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
	100	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
101	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
102	EBC_BXAP_BEM_WRITEONLY \|
103	EBC_BXAP_PEN_DISABLED);
104	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) \|
105	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
106
107	/*-------------------------------------------------------------------------+
108	\| Connector 4~7. Initialize bank 3~ 7 with default values.
109	+-------------------------------------------------------------------------*/
110	mtebc(pb4ap,0);
111	mtebc(pb4cr,0);
112	mtebc(pb5ap,0);
113	mtebc(pb5cr,0);
114	mtebc(pb6ap,0);
115	mtebc(pb6cr,0);
116	mtebc(pb7ap,0);
117	mtebc(pb7cr,0);
118
119	/*--------------------------------------------------------------------
120	* Setup the interrupt controller polarities, triggers, etc.
121	-------------------------------------------------------------------/
122	mtdcr (uic0sr, 0xffffffff); /* clear all */
123	mtdcr (uic0er, 0x00000000); /* disable all */
124	mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
125	mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
126	mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
127	mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
128	mtdcr (uic0sr, 0xffffffff); /* clear all */
129
130	mtdcr (uic1sr, 0xffffffff); /* clear all */
131	mtdcr (uic1er, 0x00000000); /* disable all */
132	mtdcr (uic1cr, 0x00000000); /* all non-critical */
133	mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
134	mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
135	mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
136	mtdcr (uic1sr, 0xffffffff); /* clear all */
137
138	mtdcr (uic2sr, 0xffffffff); /* clear all */
139	mtdcr (uic2er, 0x00000000); /* disable all */
140	mtdcr (uic2cr, 0x00000000); /* all non-critical */
141	mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
142	mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
143	mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
144	mtdcr (uic2sr, 0xffffffff); /* clear all */
145
146	mtdcr (uicb0sr, 0xfc000000); /* clear all */
147	mtdcr (uicb0er, 0x00000000); /* disable all */
148	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
149	mtdcr (uicb0pr, 0xfc000000); /* */
150	mtdcr (uicb0tr, 0x00000000); /* */
151	mtdcr (uicb0vr, 0x00000001); /* */
152
153	/* Enable two GPIO 10~11 and TraceA signal */
154	mfsdr(sdr_pfc0,reg);
155	reg \|= 0x00300000;
156	mtsdr(sdr_pfc0,reg);
157
158	mfsdr(sdr_pfc1,reg);
159	reg \|= 0x00100000;
160	mtsdr(sdr_pfc1,reg);
161
162	/* Set GPIO 10 and 11 as output */
163	GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
164	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
165	GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
166
167	*GpioOdr &= ~(0x00300000);
168	*GpioTcr \|= 0x00300000;
a4012396	169	*GpioOr \|= 0x00300000;
5fb692ca SR	170
	171	return 0;
	172	}
	173
	174	int misc_init_r(void)
	175	{
	176	lcd_init();
	177
	178	return 0;
	179	}
	180
	181	int checkboard (void)
	182	{
	183	char *s = getenv ("serial#");
	184
	185	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	186	if (s != NULL) {
	187	puts (", serial# ");
	188	puts (s);
	189	}
	190	putc ('\n');
	191
	192	#ifdef CFG_INIT_SHOW_RESET_REG
	193	show_reset_reg();
	194	#endif
	195
	196	return (0);
	197	}
	198
5fb692ca SR	199	/*************************************************************************
	200	* pci_pre_init
	201	*
	202	* This routine is called just prior to registering the hose and gives
	203	* the board the opportunity to check things. Returning a value of zero
	204	* indicates that things are bad & PCI initialization should be aborted.
	205	*
	206	* Different boards may wish to customize the pci controller structure
	207	* (add regions, override default access routines, etc) or perform
	208	* certain pre-initialization actions.
	209	*
	210	************************************************************************/
466fff1a	211	#if defined(CONFIG_PCI)
5fb692ca SR	212	int pci_pre_init(struct pci_controller * hose )
	213	{
	214	unsigned long strap;
	215
	216	/*--------------------------------------------------------------------------+
	217	* The ocotea board is always configured as the host & requires the
	218	* PCI arbiter to be enabled.
	219	--------------------------------------------------------------------------/
	220	mfsdr(sdr_sdstp1, strap);
	221	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
	222	printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
	223	return 0;
	224	}
	225
	226	return 1;
	227	}
466fff1a	228	#endif /* defined(CONFIG_PCI) */
5fb692ca SR	229
	230	/*************************************************************************
	231	* pci_target_init
	232	*
	233	* The bootstrap configuration provides default settings for the pci
	234	* inbound map (PIM). But the bootstrap config choices are limited and
	235	* may not be sufficient for a given board.
	236	*
	237	************************************************************************/
	238	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
	239	void pci_target_init(struct pci_controller * hose )
	240	{
5fb692ca SR	241	/*--------------------------------------------------------------------------+
	242	* Disable everything
	243	--------------------------------------------------------------------------/
	244	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	245	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	246	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	247	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
	248
	249	/*--------------------------------------------------------------------------+
	250	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	251	* options to not support sizes such as 128/256 MB.
	252	--------------------------------------------------------------------------/
	253	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
	254	out32r( PCIX0_PIM0LAH, 0 );
	255	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1 );
	256
	257	out32r( PCIX0_BAR0, 0 );
	258
	259	/*--------------------------------------------------------------------------+
	260	* Program the board's subsystem id/vendor id
	261	--------------------------------------------------------------------------/
	262	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
	263	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
	264
	265	out16r( PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY );
	266	}
	267	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
	268
	269	/*************************************************************************
	270	* is_pci_host
	271	*
	272	* This routine is called to determine if a pci scan should be
	273	* performed. With various hardware environments (especially cPCI and
	274	* PPMC) it's insufficient to depend on the state of the arbiter enable
	275	* bit in the strap register, or generic host/adapter assumptions.
	276	*
	277	* Rather than hard-code a bad assumption in the general 440 code, the
	278	* 440 pci code requires the board to decide at runtime.
	279	*
	280	* Return 0 for adapter mode, non-zero for host (monarch) mode.
	281	*
	282	*
	283	************************************************************************/
	284	#if defined(CONFIG_PCI)
	285	int is_pci_host(struct pci_controller *hose)
	286	{
	287	/* The ocotea board is always configured as host. */
	288	return(1);
	289	}
	290	#endif /* defined(CONFIG_PCI) */
	291
	292	#ifdef CONFIG_POST
	293	/*
	294	* Returns 1 if keys pressed to start the power-on long-running tests
	295	* Called from board_init_f().
	296	*/
	297	int post_hotkeys_pressed(void)
	298	{
	299	return (ctrlc());
	300	}
	301	#endif