[people/ms/u-boot.git] / board / amcc / taishan / taishan.c

/*
 *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
 *
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>

#ifdef CFG_INIT_SHOW_RESET_REG
void show_reset_reg(void);
#endif

int lcd_init(void);

int board_early_init_f (void)
{
	unsigned long reg;
	volatile unsigned int *GpioOdr;
	volatile unsigned int *GpioTcr;
	volatile unsigned int *GpioOr;

	/*-------------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------------*/
	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*-------------------------------------------------------------------------+
	  | 64MB FLASH. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | FPGA. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
	      EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | LCM. Initialize bank 2 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);

	/*-------------------------------------------------------------------------+
	  | TMP. Initialize bank 3 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
	      EBC_BXAP_BCE_DISABLE |
	      EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
	      EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
	      EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);
	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*-------------------------------------------------------------------------+
	  | Connector 4~7. Initialize bank 3~ 7 with default values.
	  +-------------------------------------------------------------------------*/
	mtebc(pb4ap,0);
	mtebc(pb4cr,0);
	mtebc(pb5ap,0);
	mtebc(pb5cr,0);
	mtebc(pb6ap,0);
	mtebc(pb6cr,0);
	mtebc(pb7ap,0);
	mtebc(pb7cr,0);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr (uic0sr, 0xffffffff);	/* clear all */
	mtdcr (uic0er, 0x00000000);	/* disable all */
	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic0sr, 0xffffffff);	/* clear all */

	mtdcr (uic1sr, 0xffffffff);	/* clear all */
	mtdcr (uic1er, 0x00000000);	/* disable all */
	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic1sr, 0xffffffff);	/* clear all */

	mtdcr (uic2sr, 0xffffffff);	/* clear all */
	mtdcr (uic2er, 0x00000000);	/* disable all */
	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic2sr, 0xffffffff);	/* clear all */

	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
	mtdcr (uicb0er, 0x00000000);	/* disable all */
	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
	mtdcr (uicb0pr, 0xfc000000);	/* */
	mtdcr (uicb0tr, 0x00000000);	/* */
	mtdcr (uicb0vr, 0x00000001);	/* */

	/* Enable two GPIO 10~11 and TraceA signal */
	mfsdr(sdr_pfc0,reg);
	reg |= 0x00300000;
	mtsdr(sdr_pfc0,reg);

	mfsdr(sdr_pfc1,reg);
	reg |= 0x00100000;
	mtsdr(sdr_pfc1,reg);

	/* Set GPIO 10 and 11 as output */
	GpioOdr	= (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
	GpioOr  = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);

	*GpioOdr &= ~(0x00300000);
	*GpioTcr |= 0x00300000;
	*GpioOr  |= 0x00300000;

	return 0;
}

int misc_init_r(void)
{
	lcd_init();

	return 0;
}

int checkboard (void)
{
	char *s = getenv ("serial#");

	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	if (s != NULL) {
		puts (", serial# ");
		puts (s);
	}
	putc ('\n');

#ifdef CFG_INIT_SHOW_RESET_REG
	show_reset_reg();
#endif

	return (0);
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) 0x04000000;
	uint *pend = (uint *) 0x0fc00000;
	uint *p;

	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 *	The ocotea board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(sdr_sdstp1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	DECLARE_GLOBAL_DATA_PTR;

	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	 * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
	out32r( PCIX0_PIM0LAH, 0 );
	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );

	out32r( PCIX0_BAR0, 0 );

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );

	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* The ocotea board is always configured as host. */
	return(1);
}
#endif /* defined(CONFIG_PCI) */

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return (ctrlc());
}
#endif
Commit	Line	Data
5fb692ca SR	1	/*
	2	* Copyright (C) 2004 PaulReynolds@lhsolutions.com
	3	*
	4	* (C) Copyright 2007
	5	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <asm/processor.h>
	28	#include <spd_sdram.h>
	29	#include <ppc4xx_enet.h>
	30
	31	#ifdef CFG_INIT_SHOW_RESET_REG
	32	void show_reset_reg(void);
	33	#endif
	34
	35	int lcd_init(void);
	36
	37	int board_early_init_f (void)
	38	{
	39	unsigned long reg;
	40	volatile unsigned int *GpioOdr;
	41	volatile unsigned int *GpioTcr;
	42	volatile unsigned int *GpioOr;
	43
	44	/*-------------------------------------------------------------------------+
	45	\| Initialize EBC CONFIG
	46	+-------------------------------------------------------------------------*/
	47	mtebc(xbcfg, EBC_CFG_LE_UNLOCK \|
	48	EBC_CFG_PTD_ENABLE \| EBC_CFG_RTC_64PERCLK \|
	49	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	50	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_DEFAULT \|
	51	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
	52
	53	/*-------------------------------------------------------------------------+
	54	\| 64MB FLASH. Initialize bank 0 with default values.
	55	+-------------------------------------------------------------------------*/
	56	mtebc(pb0ap, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(15) \|
	57	EBC_BXAP_BCE_DISABLE \|
	58	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
	59	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
	60	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
	61	EBC_BXAP_BEM_WRITEONLY \|
	62	EBC_BXAP_PEN_DISABLED);
	63	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) \|
	64	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_32BIT);
65
66	/*-------------------------------------------------------------------------+
67	\| FPGA. Initialize bank 1 with default values.
68	+-------------------------------------------------------------------------*/
69	mtebc(pb1ap, EBC_BXAP_BME_DISABLED\|EBC_BXAP_TWT_ENCODE(5) \|
70	EBC_BXAP_BCE_DISABLE \|
71	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_OEN_ENCODE(1) \|
72	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \|
73	EBC_BXAP_TH_ENCODE(3) \| EBC_BXAP_RE_DISABLED \|
74	EBC_BXAP_BEM_WRITEONLY \|
75	EBC_BXAP_PEN_DISABLED);
76	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) \|
77	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
78
79	/*-------------------------------------------------------------------------+
80	\| LCM. Initialize bank 2 with default values.
81	+-------------------------------------------------------------------------*/
82	mtebc(pb2ap, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(64) \|
83	EBC_BXAP_BCE_DISABLE \|
84	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
85	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
86	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
87	EBC_BXAP_BEM_WRITEONLY \|
88	EBC_BXAP_PEN_DISABLED);
89	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) \|
90	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW\|EBC_BXCR_BW_8BIT);
91
92	/*-------------------------------------------------------------------------+
93	\| TMP. Initialize bank 3 with default values.
94	+-------------------------------------------------------------------------*/
95	mtebc(pb3ap, EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(128) \|
96	EBC_BXAP_BCE_DISABLE \|
97	EBC_BXAP_CSN_ENCODE(3) \| EBC_BXAP_OEN_ENCODE(3) \|
98	EBC_BXAP_WBN_ENCODE(3) \| EBC_BXAP_WBF_ENCODE(3) \|
99	EBC_BXAP_TH_ENCODE(7) \| EBC_BXAP_RE_DISABLED \|
100	EBC_BXAP_BEM_WRITEONLY \|
101	EBC_BXAP_PEN_DISABLED);
102	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) \|
103	EBC_BXCR_BS_64MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
104
105	/*-------------------------------------------------------------------------+
106	\| Connector 4~7. Initialize bank 3~ 7 with default values.
107	+-------------------------------------------------------------------------*/
108	mtebc(pb4ap,0);
109	mtebc(pb4cr,0);
110	mtebc(pb5ap,0);
111	mtebc(pb5cr,0);
112	mtebc(pb6ap,0);
113	mtebc(pb6cr,0);
114	mtebc(pb7ap,0);
115	mtebc(pb7cr,0);
116
117	/*--------------------------------------------------------------------
118	* Setup the interrupt controller polarities, triggers, etc.
119	-------------------------------------------------------------------/
120	mtdcr (uic0sr, 0xffffffff); /* clear all */
121	mtdcr (uic0er, 0x00000000); /* disable all */
122	mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
123	mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
124	mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
125	mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
126	mtdcr (uic0sr, 0xffffffff); /* clear all */
127
128	mtdcr (uic1sr, 0xffffffff); /* clear all */
129	mtdcr (uic1er, 0x00000000); /* disable all */
130	mtdcr (uic1cr, 0x00000000); /* all non-critical */
131	mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
132	mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
133	mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
134	mtdcr (uic1sr, 0xffffffff); /* clear all */
135
136	mtdcr (uic2sr, 0xffffffff); /* clear all */
137	mtdcr (uic2er, 0x00000000); /* disable all */
138	mtdcr (uic2cr, 0x00000000); /* all non-critical */
139	mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
140	mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
141	mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
142	mtdcr (uic2sr, 0xffffffff); /* clear all */
143
144	mtdcr (uicb0sr, 0xfc000000); /* clear all */
145	mtdcr (uicb0er, 0x00000000); /* disable all */
146	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
147	mtdcr (uicb0pr, 0xfc000000); /* */
148	mtdcr (uicb0tr, 0x00000000); /* */
149	mtdcr (uicb0vr, 0x00000001); /* */
150
151	/* Enable two GPIO 10~11 and TraceA signal */
152	mfsdr(sdr_pfc0,reg);
153	reg \|= 0x00300000;
154	mtsdr(sdr_pfc0,reg);
155
156	mfsdr(sdr_pfc1,reg);
157	reg \|= 0x00100000;
158	mtsdr(sdr_pfc1,reg);
159
160	/* Set GPIO 10 and 11 as output */
161	GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
162	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
163	GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
164
165	*GpioOdr &= ~(0x00300000);
166	*GpioTcr \|= 0x00300000;
a4012396	167	*GpioOr \|= 0x00300000;
5fb692ca SR	168
	169	return 0;
	170	}
	171
	172	int misc_init_r(void)
	173	{
	174	lcd_init();
	175
	176	return 0;
	177	}
	178
	179	int checkboard (void)
	180	{
	181	char *s = getenv ("serial#");
	182
	183	printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
	184	if (s != NULL) {
	185	puts (", serial# ");
	186	puts (s);
	187	}
	188	putc ('\n');
	189
	190	#ifdef CFG_INIT_SHOW_RESET_REG
	191	show_reset_reg();
	192	#endif
	193
	194	return (0);
	195	}
	196
	197	#if defined(CFG_DRAM_TEST)
	198	int testdram (void)
	199	{
	200	uint pstart = (uint ) 0x04000000;
	201	uint pend = (uint ) 0x0fc00000;
	202	uint *p;
	203
	204	for (p = pstart; p < pend; p++)
	205	*p = 0xaaaaaaaa;
	206
	207	for (p = pstart; p < pend; p++) {
	208	if (*p != 0xaaaaaaaa) {
	209	printf ("SDRAM test fails at: %08x\n", (uint) p);
	210	return 1;
	211	}
	212	}
	213
	214	for (p = pstart; p < pend; p++)
	215	*p = 0x55555555;
	216
	217	for (p = pstart; p < pend; p++) {
	218	if (*p != 0x55555555) {
	219	printf ("SDRAM test fails at: %08x\n", (uint) p);
	220	return 1;
	221	}
	222	}
	223	return 0;
	224	}
	225	#endif
	226
	227	/*************************************************************************
	228	* pci_pre_init
	229	*
	230	* This routine is called just prior to registering the hose and gives
	231	* the board the opportunity to check things. Returning a value of zero
232	* indicates that things are bad & PCI initialization should be aborted.
233	*
234	* Different boards may wish to customize the pci controller structure
235	* (add regions, override default access routines, etc) or perform
236	* certain pre-initialization actions.
237	*
238	************************************************************************/
239	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
240	int pci_pre_init(struct pci_controller * hose )
241	{
242	unsigned long strap;
243
244	/*--------------------------------------------------------------------------+
245	* The ocotea board is always configured as the host & requires the
246	* PCI arbiter to be enabled.
247	--------------------------------------------------------------------------/
248	mfsdr(sdr_sdstp1, strap);
249	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
250	printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
251	return 0;
252	}
253
254	return 1;
255	}
256	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
257
258	/*************************************************************************
259	* pci_target_init
260	*
261	* The bootstrap configuration provides default settings for the pci
262	* inbound map (PIM). But the bootstrap config choices are limited and
263	* may not be sufficient for a given board.
264	*
265	************************************************************************/
266	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
267	void pci_target_init(struct pci_controller * hose )
268	{
269	DECLARE_GLOBAL_DATA_PTR;
270
271	/*--------------------------------------------------------------------------+
272	* Disable everything
273	--------------------------------------------------------------------------/
274	out32r( PCIX0_PIM0SA, 0 ); /* disable */
275	out32r( PCIX0_PIM1SA, 0 ); /* disable */
276	out32r( PCIX0_PIM2SA, 0 ); /* disable */
277	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
278
279	/*--------------------------------------------------------------------------+
280	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
281	* options to not support sizes such as 128/256 MB.
282	--------------------------------------------------------------------------/
283	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
284	out32r( PCIX0_PIM0LAH, 0 );
285	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1 );
286
287	out32r( PCIX0_BAR0, 0 );
288
289	/*--------------------------------------------------------------------------+
290	* Program the board's subsystem id/vendor id
291	--------------------------------------------------------------------------/
292	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
293	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
294
295	out16r( PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY );
296	}
297	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
298
299	/*************************************************************************
300	* is_pci_host
301	*
302	* This routine is called to determine if a pci scan should be
303	* performed. With various hardware environments (especially cPCI and
304	* PPMC) it's insufficient to depend on the state of the arbiter enable
305	* bit in the strap register, or generic host/adapter assumptions.
306	*
307	* Rather than hard-code a bad assumption in the general 440 code, the
308	* 440 pci code requires the board to decide at runtime.
309	*
310	* Return 0 for adapter mode, non-zero for host (monarch) mode.
311	*
312	*
313	************************************************************************/
314	#if defined(CONFIG_PCI)
315	int is_pci_host(struct pci_controller *hose)
316	{
317	/* The ocotea board is always configured as host. */
318	return(1);
319	}
320	#endif /* defined(CONFIG_PCI) */
321
322	#ifdef CONFIG_POST
323	/*
324	* Returns 1 if keys pressed to start the power-on long-running tests
325	* Called from board_init_f().
326	*/
327	int post_hotkeys_pressed(void)
328	{
329	return (ctrlc());
330	}
331	#endif