[people/ms/u-boot.git] / board / amcc / yosemite / yosemite.c

/*
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <spd_sdram.h>

DECLARE_GLOBAL_DATA_PTR;

extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/

int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */

	mtebc(pb1ap, 0x00000000);
	mtebc(pb1cr, 0x00000000);

	mtebc(pb2ap, 0x04814500);
	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */

	mtebc(pb3ap, 0x00000000);
	mtebc(pb3cr, 0x00000000);

	mtebc(pb4ap, 0x00000000);
	mtebc(pb4cr, 0x00000000);

	mtebc(pb5ap, 0x00000000);
	mtebc(pb5cr, 0x00000000);

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash size 64Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/* external interrupts IRQ0...3 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);

	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/*clear tmrclk divisor */
	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;

	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;

	/*get rid of flash write protect */
	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;

	return 0;
}

int misc_init_r (void)
{
	uint pbcr;
	int size_val = 0;

	/* Re-do sizing to get full correct info */
	mtdcr(ebccfga, pb0cr);
	pbcr = mfdcr(ebccfgd);
	switch (gd->bd->bi_flashsize) {
	case 1 << 20:
		size_val = 0;
		break;
	case 2 << 20:
		size_val = 1;
		break;
	case 4 << 20:
		size_val = 2;
		break;
	case 8 << 20:
		size_val = 3;
		break;
	case 16 << 20:
		size_val = 4;
		break;
	case 32 << 20:
		size_val = 5;
		break;
	case 64 << 20:
		size_val = 6;
		break;
	case 128 << 20:
		size_val = 7;
		break;
	}
	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
	mtdcr(ebccfga, pb0cr);
	mtdcr(ebccfgd, pbcr);

	/* adjust flash start and offset */
	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	gd->bd->bi_flashoffset = 0;

	/* Monitor protection ON by default */
	(void)flash_protect(FLAG_PROTECT_SET,
			    -CFG_MONITOR_LEN,
			    0xffffffff,
			    &flash_info[0]);

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

/*************************************************************************
 *  sdram_init -- doesn't use serial presence detect.
 *
 *  Assumes:    256 MB, ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
#define NUM_TRIES 64
#define NUM_READS 10

void sdram_tr1_set(int ram_address, int* tr1_value)
{
	int i;
	int j, k;
	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;
	int first_good = -1, last_bad = 0x1ff;

	unsigned long test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	/* go through all possible SDRAM0_TR1[RDCT] values */
	for (i=0; i<=0x1ff; i++) {
		/* set the current value for TR1 */
		mtsdram(mem_tr1, (0x80800800 | i));

		/* write values */
		for (j=0; j<NUM_TRIES; j++) {
			ram_pointer[j] = test[j];

			/* clear any cache at ram location */
			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
		}

		/* read values back */
		for (j=0; j<NUM_TRIES; j++) {
			for (k=0; k<NUM_READS; k++) {
				/* clear any cache at ram location */
				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));

				if (ram_pointer[j] != test[j])
					break;
			}

			/* read error */
			if (k != NUM_READS) {
				break;
			}
		}

		/* we have a SDRAM0_TR1[RDCT] that is part of the window */
		if (j == NUM_TRIES) {
			if (first_good == -1)
				first_good = i;		/* found beginning of window */
		} else { /* bad read */
			/* if we have not had a good read then don't care */
			if(first_good != -1) {
				/* first failure after a good read */
				last_bad = i-1;
				break;
			}
		}
	}

	/* return the current value for TR1 */
	*tr1_value = (first_good + last_bad) / 2;
}

void sdram_init(void)
{
	register uint reg;
	int tr1_bank1, tr1_bank2;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(mem_clktr, 0x40000000);	/* ?? */
	mtsdram(mem_wddctr, 0x40000000);	/* ?? */

	/*clear this first, if the DDR is enabled by a debugger
	  then you can not make changes. */
	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */

	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
	mtsdram(mem_rtr, 0x04080000);	/* ?? */
	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(mem_cfg0, 0x84000000);	/* Enable */

	for (;;) {
		mfsdram(mem_mcsts, reg);
		if (reg & 0x80000000)
			break;
	}

	sdram_tr1_set(0x00000000, &tr1_bank1);
	sdram_tr1_set(0x08000000, &tr1_bank2);
	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
}

/*************************************************************************
 *  long int initdram
 *
 ************************************************************************/
long int initdram(int board)
{
	sdram_init();
	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	unsigned long *mem = (unsigned long *)0;
	const unsigned long kend = (1024 / sizeof(unsigned long));
	unsigned long k, n;

	mtmsr(0);

	for (k = 0; k < CFG_KBYTES_SDRAM;
	     ++k, mem += (1024 / sizeof(unsigned long))) {
		if ((k & 1023) == 0) {
			printf("%3d MB\r", k / 1024);
		}

		memset(mem, 0xaaaaaaaa, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0xaaaaaaaa) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}

		memset(mem, 0x55555555, 1024);
		for (n = 0; n < kend; ++n) {
			if (mem[n] != 0x55555555) {
				printf("SDRAM test fails at: %08x\n",
				       (uint) & mem[n]);
				return 1;
			}
		}
	}
	printf("SDRAM test passes\n");
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long addr;

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB3 devices to 0.
	  | Set PLB3 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp1, addr);
	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb3_acr);
	mtdcr(plb3_acr, addr | 0x80000000);

	/*-------------------------------------------------------------------------+
	  | Set priority for all PLB4 devices to 0.
	  +-------------------------------------------------------------------------*/
	mfsdr(sdr_amp0, addr);
	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */
	mtdcr(plb4_acr, addr);

	/*-------------------------------------------------------------------------+
	  | Set Nebula PLB4 arbiter to fair mode.
	  +-------------------------------------------------------------------------*/
	/* Segment0 */
	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
	mtdcr(plb0_acr, addr);

	/* Segment1 */
	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
	mtdcr(plb1_acr, addr);

	return 1;
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	 * Set up Direct MMIO registers
	 *--------------------------------------------------------------------------*/
	/*--------------------------------------------------------------------------+
	  | PowerPC440 EP PCI Master configuration.
	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */

	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */
	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */
	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */

	/*--------------------------------------------------------------------------+
	 * Set up Configuration registers
	 *--------------------------------------------------------------------------*/

	/* Program the board's subsystem id/vendor id */
	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
			      CFG_PCI_SUBSYS_VENDORID);
	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);

	/* Configure command register as bus master */
	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);

	/* 240nS PCI clock */
	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);

	/* No error reporting */
	pci_write_config_word(0, PCI_ERREN, 0);

	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);

}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	unsigned short temp_short;

	/*--------------------------------------------------------------------------+
	  | Write the PowerPC440 EP PCI Configuration regs.
	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
	  +--------------------------------------------------------------------------*/
	pci_read_config_word(0, PCI_COMMAND, &temp_short);
	pci_write_config_word(0, PCI_COMMAND,
			      temp_short | PCI_COMMAND_MASTER |
			      PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* Bamboo is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */

/*************************************************************************
 *  hw_watchdog_reset
 *
 *	This routine is called to reset (keep alive) the watchdog timer
 *
 ************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{

}
#endif
Commit	Line	Data
c157d8e2 SR	1	/*
	2	*
	3	* See file CREDITS for list of people who contributed to this
	4	* project.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of
	9	* the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	19	* MA 02111-1307 USA
	20	*/
	21
	22	#include <common.h>
84286386	23	#include <ppc4xx.h>
c157d8e2 SR	24	#include <asm/processor.h>
	25	#include <spd_sdram.h>
	26
d87080b7 WD	27	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	28
84286386 SR	29	extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
84286386 SR	30
c157d8e2 SR	31	int board_early_init_f(void)
	32	{
	33	register uint reg;
	34
	35	/*--------------------------------------------------------------------
	36	* Setup the external bus controller/chip selects
	37	-------------------------------------------------------------------/
	38	mtdcr(ebccfga, xbcfg);
	39	reg = mfdcr(ebccfgd);
	40	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
	41
	42	mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
84286386	43	mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
c157d8e2 SR	44
	45	mtebc(pb1ap, 0x00000000);
	46	mtebc(pb1cr, 0x00000000);
	47
	48	mtebc(pb2ap, 0x04814500);
	49	/CPLD/ mtebc(pb2cr, 0x80018000); /BAS=0x800 1MB r/w 8-bit /
	50
	51	mtebc(pb3ap, 0x00000000);
	52	mtebc(pb3cr, 0x00000000);
	53
	54	mtebc(pb4ap, 0x00000000);
	55	mtebc(pb4cr, 0x00000000);
	56
	57	mtebc(pb5ap, 0x00000000);
	58	mtebc(pb5cr, 0x00000000);
	59
c157d8e2 SR	60	/*--------------------------------------------------------------------
	61	* Setup the GPIO pins
	62	-------------------------------------------------------------------/
	63	/CPLD cs /
81a3170b SR	64	/setup Address lines for flash size 64Meg. /
	65	out32(GPIO0_OSRL, in32(GPIO0_OSRL) \| 0x50010000);
	66	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x50010000);
	67	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x50000000);
c157d8e2 SR	68
	69	/setup emac /
	70	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xC080);
	71	out32(GPIO0_TSRL, in32(GPIO0_TSRL) \| 0x40);
	72	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) \| 0x55);
	73	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0x50004000);
	74	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) \| 0x00440000);
	75
	76	/UART1 /
	77	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0x02000000);
	78	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x00080000);
	79	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) \| 0x00010000);
	80
e190290b SR	81	/* external interrupts IRQ0...3 */
	82	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
	83	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
	84	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) \| 0x00005500);
	85
c157d8e2 SR	86	/setup USB 2.0 /
	87	out32(GPIO1_TCR, in32(GPIO1_TCR) \| 0xc0000000);
	88	out32(GPIO1_OSRL, in32(GPIO1_OSRL) \| 0x50000000);
	89	out32(GPIO0_TCR, in32(GPIO0_TCR) \| 0xf);
	90	out32(GPIO0_OSRH, in32(GPIO0_OSRH) \| 0xaa);
	91	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) \| 0x00000500);
	92
ef04a0aa SR	93	/*--------------------------------------------------------------------
	94	* Setup the interrupt controller polarities, triggers, etc.
	95	-------------------------------------------------------------------/
	96	mtdcr(uic0sr, 0xffffffff); /* clear all */
	97	mtdcr(uic0er, 0x00000000); /* disable all */
	98	mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
	99	mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
	100	mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
	101	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	102	mtdcr(uic0sr, 0xffffffff); /* clear all */
	103
	104	mtdcr(uic1sr, 0xffffffff); /* clear all */
	105	mtdcr(uic1er, 0x00000000); /* disable all */
	106	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	107	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
	108	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
	109	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	110	mtdcr(uic1sr, 0xffffffff); /* clear all */
	111
c157d8e2 SR	112	/*--------------------------------------------------------------------
	113	* Setup other serial configuration
	114	-------------------------------------------------------------------/
	115	mfsdr(sdr_pci0, reg);
	116	mtsdr(sdr_pci0, 0x80000000 \| reg); /* PCI arbiter enabled */
	117	mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
	118	mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
	119
	120	/clear tmrclk divisor /
	121	(unsigned char )(CFG_BCSR_BASE \| 0x04) = 0x00;
	122
	123	/enable ethernet /
	124	(unsigned char )(CFG_BCSR_BASE \| 0x08) = 0xf0;
	125
	126	/enable usb 1.1 fs device and remove usb 2.0 reset /
	127	(unsigned char )(CFG_BCSR_BASE \| 0x09) = 0x00;
	128
	129	/get rid of flash write protect /
81a3170b	130	(unsigned char )(CFG_BCSR_BASE \| 0x07) = 0x00;
c157d8e2 SR	131
	132	return 0;
	133	}
	134
84286386 SR	135	int misc_init_r (void)
84286386 SR	136	{
84286386 SR	137	uint pbcr;
	138	int size_val = 0;
	139
	140	/* Re-do sizing to get full correct info */
	141	mtdcr(ebccfga, pb0cr);
	142	pbcr = mfdcr(ebccfgd);
	143	switch (gd->bd->bi_flashsize) {
	144	case 1 << 20:
	145	size_val = 0;
	146	break;
	147	case 2 << 20:
	148	size_val = 1;
	149	break;
	150	case 4 << 20:
	151	size_val = 2;
	152	break;
	153	case 8 << 20:
	154	size_val = 3;
	155	break;
	156	case 16 << 20:
	157	size_val = 4;
	158	break;
	159	case 32 << 20:
	160	size_val = 5;
	161	break;
	162	case 64 << 20:
	163	size_val = 6;
	164	break;
	165	case 128 << 20:
	166	size_val = 7;
	167	break;
	168	}
	169	pbcr = (pbcr & 0x0001ffff) \| gd->bd->bi_flashstart \| (size_val << 17);
	170	mtdcr(ebccfga, pb0cr);
	171	mtdcr(ebccfgd, pbcr);
	172
f190c11b SR	173	/* adjust flash start and offset */
	174	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
	175	gd->bd->bi_flashoffset = 0;
	176
84286386 SR	177	/* Monitor protection ON by default */
	178	(void)flash_protect(FLAG_PROTECT_SET,
	179	-CFG_MONITOR_LEN,
	180	0xffffffff,
	181	&flash_info[0]);
	182
	183	return 0;
	184	}
	185
c157d8e2 SR	186	int checkboard(void)
c157d8e2 SR	187	{
3d9569b2	188	char *s = getenv("serial#");
c157d8e2	189
93b17ec3 SR	190	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
	191	if (s != NULL) {
	192	puts(", serial# ");
	193	puts(s);
	194	}
	195	putc('\n');
	196
c157d8e2 SR	197	return (0);
	198	}
	199
	200	/*************************************************************************
	201	* sdram_init -- doesn't use serial presence detect.
	202	*
	203	* Assumes: 256 MB, ECC, non-registered
	204	* PLB @ 133 MHz
	205	*
	206	************************************************************************/
81a3170b SR	207	#define NUM_TRIES 64
	208	#define NUM_READS 10
	209
	210	void sdram_tr1_set(int ram_address, int* tr1_value)
	211	{
	212	int i;
	213	int j, k;
	214	volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
	215	int first_good = -1, last_bad = 0x1ff;
	216
	217	unsigned long test[NUM_TRIES] = {
	218	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	219	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
	220	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	221	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
	222	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	223	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
	224	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	225	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
	226	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	227	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
	228	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	229	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
	230	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	231	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
	232	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
	233	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
	234
	235	/* go through all possible SDRAM0_TR1[RDCT] values */
	236	for (i=0; i<=0x1ff; i++) {
	237	/* set the current value for TR1 */
	238	mtsdram(mem_tr1, (0x80800800 \| i));
	239
	240	/* write values */
	241	for (j=0; j<NUM_TRIES; j++) {
	242	ram_pointer[j] = test[j];
	243
	244	/* clear any cache at ram location */
	245	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	246	}
	247
	248	/* read values back */
	249	for (j=0; j<NUM_TRIES; j++) {
	250	for (k=0; k<NUM_READS; k++) {
	251	/* clear any cache at ram location */
	252	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
	253
	254	if (ram_pointer[j] != test[j])
	255	break;
	256	}
	257
	258	/* read error */
	259	if (k != NUM_READS) {
	260	break;
	261	}
	262	}
	263
	264	/* we have a SDRAM0_TR1[RDCT] that is part of the window */
	265	if (j == NUM_TRIES) {
	266	if (first_good == -1)
	267	first_good = i; /* found beginning of window */
	268	} else { /* bad read */
	269	/* if we have not had a good read then don't care */
	270	if(first_good != -1) {
271	/* first failure after a good read */
272	last_bad = i-1;
273	break;
274	}
275	}
276	}
277
278	/* return the current value for TR1 */
279	*tr1_value = (first_good + last_bad) / 2;
280	}
281
c157d8e2 SR	282	void sdram_init(void)
	283	{
	284	register uint reg;
81a3170b	285	int tr1_bank1, tr1_bank2;
c157d8e2 SR	286
	287	/*--------------------------------------------------------------------
	288	* Setup some default
	289	------------------------------------------------------------------/
	290	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	291	mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	292	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	293	mtsdram(mem_clktr, 0x40000000); /* ?? */
	294	mtsdram(mem_wddctr, 0x40000000); /* ?? */
	295
	296	/*clear this first, if the DDR is enabled by a debugger
81a3170b	297	then you can not make changes. */
c157d8e2 SR	298	mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
	299
	300	/*--------------------------------------------------------------------
	301	* Setup for board-specific specific mem
	302	------------------------------------------------------------------/
	303	/*
	304	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	305	*/
	306	mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
	307	mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
	308
	309	mtsdram(mem_tr0, 0x410a4012); /* ?? */
c157d8e2 SR	310	mtsdram(mem_rtr, 0x04080000); /* ?? */
	311	mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
	312	mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
	313	udelay(400); /* Delay 200 usecs (min) */
	314
	315	/*--------------------------------------------------------------------
	316	* Enable the controller, then wait for DCEN to complete
	317	------------------------------------------------------------------/
	318	mtsdram(mem_cfg0, 0x84000000); /* Enable */
	319
	320	for (;;) {
	321	mfsdram(mem_mcsts, reg);
	322	if (reg & 0x80000000)
	323	break;
	324	}
81a3170b SR	325
	326	sdram_tr1_set(0x00000000, &tr1_bank1);
	327	sdram_tr1_set(0x08000000, &tr1_bank2);
	328	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) \| 0x80800800) );
c157d8e2 SR	329	}
	330
	331	/*************************************************************************
	332	* long int initdram
	333	*
	334	************************************************************************/
	335	long int initdram(int board)
	336	{
	337	sdram_init();
	338	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
	339	}
	340
	341	#if defined(CFG_DRAM_TEST)
	342	int testdram(void)
	343	{
	344	unsigned long mem = (unsigned long )0;
	345	const unsigned long kend = (1024 / sizeof(unsigned long));
	346	unsigned long k, n;
	347
	348	mtmsr(0);
	349
	350	for (k = 0; k < CFG_KBYTES_SDRAM;
	351	++k, mem += (1024 / sizeof(unsigned long))) {
	352	if ((k & 1023) == 0) {
	353	printf("%3d MB\r", k / 1024);
	354	}
	355
	356	memset(mem, 0xaaaaaaaa, 1024);
	357	for (n = 0; n < kend; ++n) {
	358	if (mem[n] != 0xaaaaaaaa) {
	359	printf("SDRAM test fails at: %08x\n",
	360	(uint) & mem[n]);
	361	return 1;
	362	}
	363	}
	364
	365	memset(mem, 0x55555555, 1024);
	366	for (n = 0; n < kend; ++n) {
	367	if (mem[n] != 0x55555555) {
	368	printf("SDRAM test fails at: %08x\n",
	369	(uint) & mem[n]);
	370	return 1;
	371	}
	372	}
	373	}
	374	printf("SDRAM test passes\n");
	375	return 0;
	376	}
	377	#endif
	378
	379	/*************************************************************************
	380	* pci_pre_init
	381	*
	382	* This routine is called just prior to registering the hose and gives
	383	* the board the opportunity to check things. Returning a value of zero
	384	* indicates that things are bad & PCI initialization should be aborted.
	385	*
	386	* Different boards may wish to customize the pci controller structure
	387	* (add regions, override default access routines, etc) or perform
	388	* certain pre-initialization actions.
	389	*
	390	************************************************************************/
	391	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
	392	int pci_pre_init(struct pci_controller *hose)
393	{
c157d8e2 SR	394	unsigned long addr;
c157d8e2 SR	395
c157d8e2 SR	396	/*-------------------------------------------------------------------------+
	397	\| Set priority for all PLB3 devices to 0.
	398	\| Set PLB3 arbiter to fair mode.
	399	+-------------------------------------------------------------------------*/
	400	mfsdr(sdr_amp1, addr);
	401	mtsdr(sdr_amp1, (addr & 0x000000FF) \| 0x0000FF00);
	402	addr = mfdcr(plb3_acr);
	403	mtdcr(plb3_acr, addr \| 0x80000000);
	404
	405	/*-------------------------------------------------------------------------+
	406	\| Set priority for all PLB4 devices to 0.
	407	+-------------------------------------------------------------------------*/
	408	mfsdr(sdr_amp0, addr);
	409	mtsdr(sdr_amp0, (addr & 0x000000FF) \| 0x0000FF00);
	410	addr = mfdcr(plb4_acr) \| 0xa0000000; /* Was 0x8---- */
	411	mtdcr(plb4_acr, addr);
	412
	413	/*-------------------------------------------------------------------------+
	414	\| Set Nebula PLB4 arbiter to fair mode.
	415	+-------------------------------------------------------------------------*/
	416	/* Segment0 */
	417	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) \| plb0_acr_ppm_fair;
	418	addr = (addr & ~plb0_acr_hbu_mask) \| plb0_acr_hbu_enabled;
	419	addr = (addr & ~plb0_acr_rdp_mask) \| plb0_acr_rdp_4deep;
	420	addr = (addr & ~plb0_acr_wrp_mask) \| plb0_acr_wrp_2deep;
	421	mtdcr(plb0_acr, addr);
	422
	423	/* Segment1 */
	424	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) \| plb1_acr_ppm_fair;
	425	addr = (addr & ~plb1_acr_hbu_mask) \| plb1_acr_hbu_enabled;
	426	addr = (addr & ~plb1_acr_rdp_mask) \| plb1_acr_rdp_4deep;
	427	addr = (addr & ~plb1_acr_wrp_mask) \| plb1_acr_wrp_2deep;
	428	mtdcr(plb1_acr, addr);
	429
	430	return 1;
	431	}
	432	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
	433
	434	/*************************************************************************
	435	* pci_target_init
	436	*
	437	* The bootstrap configuration provides default settings for the pci
	438	* inbound map (PIM). But the bootstrap config choices are limited and
	439	* may not be sufficient for a given board.
	440	*
	441	************************************************************************/
	442	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
	443	void pci_target_init(struct pci_controller *hose)
	444	{
	445	/*--------------------------------------------------------------------------+
	446	* Set up Direct MMIO registers
	447	--------------------------------------------------------------------------/
	448	/*--------------------------------------------------------------------------+
	449	\| PowerPC440 EP PCI Master configuration.
	450	\| Map one 1Gig range of PLB/processor addresses to PCI memory space.
	451	\| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
	452	\| Use byte reversed out routines to handle endianess.
	453	\| Make this region non-prefetchable.
	454	+--------------------------------------------------------------------------*/
	455	out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
	456	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
	457	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
	458	out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
	459	out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
460
461	out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
462	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
463	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
464	out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
465	out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
466
467	out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
468	out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
469	out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
470	out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
471
472	/*--------------------------------------------------------------------------+
473	* Set up Configuration registers
474	--------------------------------------------------------------------------/
475
476	/* Program the board's subsystem id/vendor id */
477	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
478	CFG_PCI_SUBSYS_VENDORID);
479	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
480
481	/* Configure command register as bus master */
482	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
483
484	/* 240nS PCI clock */
485	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
486
487	/* No error reporting */
488	pci_write_config_word(0, PCI_ERREN, 0);
489
490	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
491
492	}
493	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
494
495	/*************************************************************************
496	* pci_master_init
497	*
498	************************************************************************/
499	#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
500	void pci_master_init(struct pci_controller *hose)
501	{
502	unsigned short temp_short;
503
504	/*--------------------------------------------------------------------------+
505	\| Write the PowerPC440 EP PCI Configuration regs.
506	\| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
507	\| Enable PowerPC440 EP to act as a PCI memory target (PTM).
508	+--------------------------------------------------------------------------*/
509	pci_read_config_word(0, PCI_COMMAND, &temp_short);
510	pci_write_config_word(0, PCI_COMMAND,
511	temp_short \| PCI_COMMAND_MASTER \|
512	PCI_COMMAND_MEMORY);
513	}
514	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
515
516	/*************************************************************************
517	* is_pci_host
518	*
519	* This routine is called to determine if a pci scan should be
520	* performed. With various hardware environments (especially cPCI and
521	* PPMC) it's insufficient to depend on the state of the arbiter enable
522	* bit in the strap register, or generic host/adapter assumptions.
523	*
524	* Rather than hard-code a bad assumption in the general 440 code, the
525	* 440 pci code requires the board to decide at runtime.
526	*
527	* Return 0 for adapter mode, non-zero for host (monarch) mode.
528	*
529	*
530	************************************************************************/
531	#if defined(CONFIG_PCI)
532	int is_pci_host(struct pci_controller *hose)
533	{
534	/* Bamboo is always configured as host. */
535	return (1);
536	}
537	#endif /* defined(CONFIG_PCI) */
538
539	/*************************************************************************
540	* hw_watchdog_reset
541	*
542	* This routine is called to reset (keep alive) the watchdog timer
543	*
544	************************************************************************/
545	#if defined(CONFIG_HW_WATCHDOG)
546	void hw_watchdog_reset(void)
547	{
548
549	}
550	#endif