[thirdparty/u-boot.git] / board / aristainetos / aristainetos.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * Based on:
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 */

#include <common.h>
#include <bmp_layout.h>
#include <command.h>
#include <image.h>
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/global_data.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/video.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/sections.h>
#include <bmp_logo.h>
#include <dm/root.h>
#include <env.h>
#include <i2c_eeprom.h>
#include <i2c.h>
#include <micrel.h>
#include <miiphy.h>
#include <led.h>
#include <power/pmic.h>
#include <power/regulator.h>
#include <power/da9063_pmic.h>
#include <splash.h>
#include <video.h>

DECLARE_GLOBAL_DATA_PTR;

enum {
	BOARD_TYPE_4 = 4,
	BOARD_TYPE_7 = 7,
};

#define ARI_BT_4 "aristainetos2_4@2"
#define ARI_BT_7 "aristainetos2_7@1"

int board_phy_config(struct phy_device *phydev)
{
	/* control data pad skew - devaddr = 0x02, register = 0x04 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
	ksz9031_phy_extended_write(phydev, 0x02,
				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

static int rotate_logo_one(unsigned char *out, unsigned char *in)
{
	int   i, j;

	for (i = 0; i < BMP_LOGO_WIDTH; i++)
		for (j = 0; j < BMP_LOGO_HEIGHT; j++)
			out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
			in[i * BMP_LOGO_WIDTH + j];
	return 0;
}

/*
 * Rotate the BMP_LOGO (only)
 * Will only work, if the logo is square, as
 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 */
void rotate_logo(int rotations)
{
	unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
	struct bmp_header *header;
	unsigned char *in_logo;
	int   i, j;

	if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
		return;

	header = (struct bmp_header *)bmp_logo_bitmap;
	in_logo = bmp_logo_bitmap + header->data_offset;

	/* one 90 degree rotation */
	if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
		rotate_logo_one(out_logo, in_logo);

	/* second 90 degree rotation */
	if (rotations == 2  ||  rotations == 3)
		rotate_logo_one(in_logo, out_logo);

	/* third 90 degree rotation */
	if (rotations == 3)
		rotate_logo_one(out_logo, in_logo);

	/* copy result back to original array */
	if (rotations == 1  ||  rotations == 3)
		for (i = 0; i < BMP_LOGO_WIDTH; i++)
			for (j = 0; j < BMP_LOGO_HEIGHT; j++)
				in_logo[i * BMP_LOGO_WIDTH + j] =
				out_logo[i * BMP_LOGO_WIDTH + j];
}

static void enable_lvds(struct display_info_t const *dev)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;
	s32 timeout = 100000;

	/* set PLL5 clock */
	reg = readl(&ccm->analog_pll_video);
	reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
	writel(reg, &ccm->analog_pll_video);

	/* set PLL5 to 232720000Hz */
	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
	reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
	reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
	writel(reg, &ccm->analog_pll_video);

	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
	       &ccm->analog_pll_video_num);
	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
	       &ccm->analog_pll_video_denom);

	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
	writel(reg, &ccm->analog_pll_video);

	while (timeout--)
		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
			break;
	if (timeout < 0)
		printf("Warning: video pll lock timeout!\n");

	reg = readl(&ccm->analog_pll_video);
	reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
	writel(reg, &ccm->analog_pll_video);

	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
	reg = readl(&ccm->cs2cdr);
	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
		 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
	reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
		| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
	writel(reg, &ccm->cs2cdr);

	reg = readl(&ccm->cscmr2);
	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
	writel(reg, &ccm->cscmr2);

	reg = readl(&ccm->chsccdr);
	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	writel(reg, &ccm->chsccdr);

	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
	      | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
	      | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
	      | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
	      | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
	      | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
	      | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
	writel(reg, &iomux->gpr[2]);

	reg = readl(&iomux->gpr[3]);
	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
	       | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
		  << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
	writel(reg, &iomux->gpr[3]);
}

static void setup_display(void)
{
	enable_ipu_clock();
}

static void set_gpr_register(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
	       IOMUXC_GPR1_EXC_MON_SLVE |
	       (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
	       IOMUXC_GPR1_ACT_CS0,
	       &iomuxc_regs->gpr[1]);
	writel(0x0, &iomuxc_regs->gpr[8]);
	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
	       IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
	       &iomuxc_regs->gpr[12]);
}

int board_early_init_f(void)
{
	select_ldb_di_clock_source(MXC_PLL5_CLK);
	set_gpr_register();

	/*
	 * clear bss here, so we can use spi driver
	 * before relocation and read Environment
	 * from spi flash.
	 */
	memset(__bss_start, 0x00, __bss_end - __bss_start);

	return 0;
}

static void setup_one_led(char *label, int state)
{
	struct udevice *dev;
	int ret;

	ret = led_get_by_label(label, &dev);
	if (ret == 0)
		led_set_state(dev, state);
}

static void setup_board_gpio(void)
{
	setup_one_led("led_ena", LEDST_ON);
	/* switch off Status LEDs */
	setup_one_led("led_yellow", LEDST_OFF);
	setup_one_led("led_red", LEDST_OFF);
	setup_one_led("led_green", LEDST_OFF);
	setup_one_led("led_blue", LEDST_OFF);
}

static void aristainetos_run_rescue_command(int reason)
{
	char rescue_reason_command[20];

	sprintf(rescue_reason_command, "setenv rreason %d", reason);
	run_command(rescue_reason_command, 0);
}

static int aristainetos_bootmode_settings(void)
{
	struct gpio_desc *desc;
	struct src *psrc = (struct src *)SRC_BASE_ADDR;
	unsigned int sbmr1 = readl(&psrc->sbmr1);
	char *my_bootdelay;
	char bootmode = 0;
	int ret;
	struct udevice *dev;
	int off;
	u8 data[0x10];
	u8 rescue_reason;

	/* jumper controlled reset of the environment */
	ret = gpio_hog_lookup_name("env_reset", &desc);
	if (!ret) {
		if (dm_gpio_get_value(desc)) {
			printf("\nReset u-boot environment (jumper)\n");
			run_command("run default_env; saveenv; saveenv", 0);
		}
	}

	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
	if (off < 0) {
		printf("%s: No eeprom0 path offset\n", __func__);
		return off;
	}

	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
	if (ret) {
		printf("%s: Could not find EEPROM\n", __func__);
		return ret;
	}

	ret = i2c_set_chip_offset_len(dev, 2);
	if (ret)
		return ret;

	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
	if (ret) {
		printf("%s: Could not read EEPROM\n", __func__);
		return ret;
	}

	/* software controlled reset of the environment (EEPROM magic) */
	if (strncmp((char *)data, "DeF", 3) == 0) {
		memset(data, 0xff, 3);
		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
		printf("\nReset u-boot environment (EEPROM)\n");
		run_command("run default_env; saveenv; saveenv", 0);
	}

	if (sbmr1 & 0x40) {
		env_set("bootmode", "1");
		printf("SD bootmode jumper set!\n");
	} else {
		env_set("bootmode", "0");
	}

	/*
	 * Check the boot-source. If booting from NOR Flash,
	 * disable bootdelay
	 */
	ret = gpio_hog_lookup_name("bootsel0", &desc);
	if (!ret)
		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
	ret = gpio_hog_lookup_name("bootsel1", &desc);
	if (!ret)
		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
	ret = gpio_hog_lookup_name("bootsel2", &desc);
	if (!ret)
		bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;

	if (bootmode == 7) {
		my_bootdelay = env_get("nor_bootdelay");
		if (my_bootdelay)
			env_set("bootdelay", my_bootdelay);
		else
			env_set("bootdelay", "-2");
	}

	/* jumper controlled boot of the rescue system */
	ret = gpio_hog_lookup_name("boot_rescue", &desc);
	if (!ret) {
		if (dm_gpio_get_value(desc)) {
			printf("\nBooting into Rescue System (jumper)\n");
			aristainetos_run_rescue_command(16);
			run_command("run rescue_xload_boot", 0);
		}
	}

	/* software controlled boot of the rescue system (EEPROM magic) */
	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
		rescue_reason = *(uint8_t *)&data[9];
		memset(&data[3], 0xff, 7);
		i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
		printf("\nBooting into Rescue System (EEPROM)\n");
		aristainetos_run_rescue_command(rescue_reason);
		run_command("run rescue_xload_boot", 0);
	}

	return 0;
}

#if defined(CONFIG_DM_PMIC_DA9063)
/*
 * On the aristainetos2c boards the PMIC needs to be initialized,
 * because the Ethernet PHY uses a different regulator that is not
 * setup per hardware default. This does not influence the other versions
 * as this regulator isn't used there at all.
 *
 * Unfortunately we have not yet a interface to setup all
 * values we need.
 */
static int setup_pmic_voltages(void)
{
	struct udevice *dev;
	int off;
	int ret;

	off = fdt_path_offset(gd->fdt_blob, "pmic0");
	if (off < 0) {
		printf("%s: No pmic path offset\n", __func__);
		return off;
	}

	ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
	if (ret) {
		printf("%s: Could not find PMIC\n", __func__);
		return ret;
	}

	pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
	pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
	ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
	if (ret < 0) {
		printf("%s: error %d get register\n", __func__, ret);
		return ret;
	}
	ret &= 0xf0;
	ret |= 0x09;
	pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
	pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
	pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);

	return 0;
}
#else
static int setup_pmic_voltages(void)
{
	return 0;
}
#endif

int board_late_init(void)
{
	int x, y;
	int ret;

	splash_get_pos(&x, &y);
	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);

	ret = aristainetos_bootmode_settings();
	if (ret)
		return ret;

	/* set board_type */
	if (gd->board_type == BOARD_TYPE_4)
		env_set("board_type", ARI_BT_4);
	else
		env_set("board_type", ARI_BT_7);

	if (setup_pmic_voltages())
		printf("Error setup PMIC\n");

	return 0;
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();

	return 0;
}

struct display_info_t const displays[] = {
	{
		.bus	= -1,
		.addr	= 0,
		.pixfmt	= IPU_PIX_FMT_RGB24,
		.detect	= NULL,
		.enable	= enable_lvds,
		.mode	= {
			.name           = "lb07wv8",
			.refresh        = 60,
			.xres           = 800,
			.yres           = 480,
			.pixclock       = 30066,
			.left_margin    = 88,
			.right_margin   = 88,
			.upper_margin   = 20,
			.lower_margin   = 20,
			.hsync_len      = 80,
			.vsync_len      = 5,
			.sync           = FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}
};
size_t display_count = ARRAY_SIZE(displays);

int board_init(void)
{
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	setup_board_gpio();
	setup_display();

	/* GPIO_1 for USB_OTG_ID */
	clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
	return 0;
}

int board_fit_config_name_match(const char *name)
{
	if (gd->board_type == BOARD_TYPE_4 &&
	    strchr(name, 0x34))
		return 0;

	if (gd->board_type == BOARD_TYPE_7 &&
	    strchr(name, 0x37))
		return 0;

	return -1;
}

static void do_board_detect(void)
{
	int ret;
	char s[30];

	/* default use board type 7 */
	gd->board_type = BOARD_TYPE_7;
	if (env_init())
		return;

	ret = env_get_f("panel", s, sizeof(s));
	if (ret < 0)
		return;

	if (!strncmp("lg4573", s, 6))
		gd->board_type = BOARD_TYPE_4;
}

#ifdef CONFIG_DTB_RESELECT
int embedded_dtb_select(void)
{
	int rescan;

	do_board_detect();
	fdtdec_resetup(&rescan);

	return 0;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
e379c039 HS	2	/*
	3	* (C) Copyright 2014
	4	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	5	*
	6	* Based on:
	7	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	8	*
	9	* Author: Fabio Estevam <fabio.estevam@freescale.com>
e379c039 HS	10	*/
e379c039 HS	11
d678a59d	12	#include <common.h>
70cc7b61	13	#include <bmp_layout.h>
09140113	14	#include <command.h>
4d72caa5	15	#include <image.h>
691d719d	16	#include <init.h>
e379c039 HS	17	#include <asm/arch/clock.h>
	18	#include <asm/arch/imx-regs.h>
	19	#include <asm/arch/iomux.h>
	20	#include <asm/arch/mx6-pins.h>
401d1c4f	21	#include <asm/global_data.h>
1221ce45	22	#include <linux/errno.h>
e379c039	23	#include <asm/gpio.h>
552a848e SB	24	#include <asm/mach-imx/iomux-v3.h>
552a848e SB	25	#include <asm/mach-imx/boot_mode.h>
552a848e	26	#include <asm/mach-imx/video.h>
e379c039	27	#include <asm/arch/crm_regs.h>
e379c039 HS	28	#include <asm/io.h>
e379c039 HS	29	#include <asm/arch/sys_proto.h>
506df9dc	30	#include <asm/sections.h>
621ff136	31	#include <bmp_logo.h>
ccc7595a	32	#include <dm/root.h>
0f1130b6	33	#include <env.h>
f7cf76f8 HS	34	#include <i2c_eeprom.h>
f7cf76f8 HS	35	#include <i2c.h>
0f1130b6	36	#include <micrel.h>
5e65496d	37	#include <miiphy.h>
fc7e3cc6	38	#include <led.h>
158d93ad HS	39	#include <power/pmic.h>
	40	#include <power/regulator.h>
	41	#include <power/da9063_pmic.h>
621ff136	42	#include <splash.h>
70cc7b61	43	#include <video.h>
e379c039 HS	44
	45	DECLARE_GLOBAL_DATA_PTR;
	46
ccc7595a HS	47	enum {
	48	BOARD_TYPE_4 = 4,
	49	BOARD_TYPE_7 = 7,
	50	};
	51
	52	#define ARI_BT_4 "aristainetos2_4@2"
	53	#define ARI_BT_7 "aristainetos2_7@1"
	54
0f1130b6 HS	55	int board_phy_config(struct phy_device *phydev)
	56	{
	57	/* control data pad skew - devaddr = 0x02, register = 0x04 */
	58	ksz9031_phy_extended_write(phydev, 0x02,
	59	MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
	60	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	61	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
	62	ksz9031_phy_extended_write(phydev, 0x02,
	63	MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
	64	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	65	/* tx data pad skew - devaddr = 0x02, register = 0x06 */
	66	ksz9031_phy_extended_write(phydev, 0x02,
	67	MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
	68	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
	69	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
	70	ksz9031_phy_extended_write(phydev, 0x02,
	71	MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
	72	MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
	73
	74	if (phydev->drv->config)
	75	phydev->drv->config(phydev);
	76
	77	return 0;
	78	}
	79
0f1130b6 HS	80	static int rotate_logo_one(unsigned char out, unsigned char in)
	81	{
	82	int i, j;
	83
	84	for (i = 0; i < BMP_LOGO_WIDTH; i++)
	85	for (j = 0; j < BMP_LOGO_HEIGHT; j++)
	86	out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
	87	in[i * BMP_LOGO_WIDTH + j];
	88	return 0;
	89	}
	90
	91	/*
	92	* Rotate the BMP_LOGO (only)
	93	* Will only work, if the logo is square, as
	94	* BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
	95	*/
	96	void rotate_logo(int rotations)
	97	{
	98	unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
621ff136	99	struct bmp_header *header;
0f1130b6 HS	100	unsigned char *in_logo;
	101	int i, j;
	102
	103	if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
	104	return;
	105
621ff136 HS	106	header = (struct bmp_header *)bmp_logo_bitmap;
621ff136 HS	107	in_logo = bmp_logo_bitmap + header->data_offset;
0f1130b6 HS	108
	109	/* one 90 degree rotation */
	110	if (rotations == 1 \|\| rotations == 2 \|\| rotations == 3)
	111	rotate_logo_one(out_logo, in_logo);
	112
	113	/* second 90 degree rotation */
	114	if (rotations == 2 \|\| rotations == 3)
	115	rotate_logo_one(in_logo, out_logo);
	116
	117	/* third 90 degree rotation */
	118	if (rotations == 3)
	119	rotate_logo_one(out_logo, in_logo);
	120
	121	/* copy result back to original array */
	122	if (rotations == 1 \|\| rotations == 3)
	123	for (i = 0; i < BMP_LOGO_WIDTH; i++)
	124	for (j = 0; j < BMP_LOGO_HEIGHT; j++)
	125	in_logo[i * BMP_LOGO_WIDTH + j] =
	126	out_logo[i * BMP_LOGO_WIDTH + j];
	127	}
	128
0f1130b6 HS	129	static void enable_lvds(struct display_info_t const *dev)
	130	{
	131	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	132	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	133	int reg;
	134	s32 timeout = 100000;
	135
	136	/* set PLL5 clock */
	137	reg = readl(&ccm->analog_pll_video);
	138	reg \|= BM_ANADIG_PLL_VIDEO_POWERDOWN;
	139	writel(reg, &ccm->analog_pll_video);
	140
	141	/* set PLL5 to 232720000Hz */
	142	reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
	143	reg \|= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
	144	reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
	145	reg \|= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
	146	writel(reg, &ccm->analog_pll_video);
	147
	148	writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
	149	&ccm->analog_pll_video_num);
	150	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
	151	&ccm->analog_pll_video_denom);
	152
	153	reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
	154	writel(reg, &ccm->analog_pll_video);
	155
	156	while (timeout--)
	157	if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
	158	break;
	159	if (timeout < 0)
	160	printf("Warning: video pll lock timeout!\n");
	161
	162	reg = readl(&ccm->analog_pll_video);
	163	reg \|= BM_ANADIG_PLL_VIDEO_ENABLE;
	164	reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
	165	writel(reg, &ccm->analog_pll_video);
	166
	167	/* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
	168	reg = readl(&ccm->cs2cdr);
	169	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
	170	\| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
	171	reg \|= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
	172	\| (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
	173	writel(reg, &ccm->cs2cdr);
	174
	175	reg = readl(&ccm->cscmr2);
	176	reg \|= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
	177	writel(reg, &ccm->cscmr2);
	178
	179	reg = readl(&ccm->chsccdr);
	180	reg \|= (CHSCCDR_CLK_SEL_LDB_DI0
	181	<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
	182	writel(reg, &ccm->chsccdr);
	183
	184	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
	185	\| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
	186	\| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
	187	\| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
	188	\| IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
	189	\| IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
	190	\| IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
	191	writel(reg, &iomux->gpr[2]);
	192
193	reg = readl(&iomux->gpr[3]);
194	reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
195	\| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
196	<< IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
197	writel(reg, &iomux->gpr[3]);
198	}
199
0f1130b6 HS	200	static void setup_display(void)
	201	{
	202	enable_ipu_clock();
0f1130b6 HS	203	}
0f1130b6 HS	204
0f1130b6 HS	205	static void set_gpr_register(void)
	206	{
	207	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	208
	209	writel(IOMUXC_GPR1_APP_CLK_REQ_N \| IOMUXC_GPR1_PCIE_RDY_L23 \|
	210	IOMUXC_GPR1_EXC_MON_SLVE \|
	211	(2 << IOMUXC_GPR1_ADDRS0_OFFSET) \|
	212	IOMUXC_GPR1_ACT_CS0,
	213	&iomuxc_regs->gpr[1]);
	214	writel(0x0, &iomuxc_regs->gpr[8]);
	215	writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN \| IOMUXC_GPR12_ARMP_AHB_CLK_EN \|
	216	IOMUXC_GPR12_ARMP_ATB_CLK_EN \| IOMUXC_GPR12_ARMP_APB_CLK_EN,
	217	&iomuxc_regs->gpr[12]);
	218	}
	219
	220	int board_early_init_f(void)
	221	{
621ff136	222	select_ldb_di_clock_source(MXC_PLL5_CLK);
0f1130b6	223	set_gpr_register();
ccc7595a HS	224
	225	/*
	226	* clear bss here, so we can use spi driver
	227	* before relocation and read Environment
	228	* from spi flash.
	229	*/
	230	memset(__bss_start, 0x00, __bss_end - __bss_start);
	231
0f1130b6 HS	232	return 0;
	233	}
	234
fc7e3cc6	235	static void setup_one_led(char *label, int state)
0f1130b6	236	{
fc7e3cc6 HS	237	struct udevice *dev;
fc7e3cc6 HS	238	int ret;
0f1130b6	239
fc7e3cc6 HS	240	ret = led_get_by_label(label, &dev);
	241	if (ret == 0)
	242	led_set_state(dev, state);
	243	}
	244
	245	static void setup_board_gpio(void)
	246	{
	247	setup_one_led("led_ena", LEDST_ON);
0f1130b6	248	/* switch off Status LEDs */
fc7e3cc6 HS	249	setup_one_led("led_yellow", LEDST_OFF);
	250	setup_one_led("led_red", LEDST_OFF);
	251	setup_one_led("led_green", LEDST_OFF);
	252	setup_one_led("led_blue", LEDST_OFF);
0f1130b6 HS	253	}
0f1130b6 HS	254
f7cf76f8 HS	255	static void aristainetos_run_rescue_command(int reason)
f7cf76f8 HS	256	{
3cf02f5f	257	char rescue_reason_command[20];
f7cf76f8	258
3cf02f5f	259	sprintf(rescue_reason_command, "setenv rreason %d", reason);
f7cf76f8 HS	260	run_command(rescue_reason_command, 0);
	261	}
	262
3cf02f5f	263	static int aristainetos_bootmode_settings(void)
f7cf76f8	264	{
3cf02f5f HS	265	struct gpio_desc *desc;
	266	struct src psrc = (struct src )SRC_BASE_ADDR;
	267	unsigned int sbmr1 = readl(&psrc->sbmr1);
	268	char *my_bootdelay;
	269	char bootmode = 0;
	270	int ret;
f7cf76f8 HS	271	struct udevice *dev;
f7cf76f8 HS	272	int off;
f7cf76f8 HS	273	u8 data[0x10];
	274	u8 rescue_reason;
	275
3cf02f5f HS	276	/* jumper controlled reset of the environment */
	277	ret = gpio_hog_lookup_name("env_reset", &desc);
	278	if (!ret) {
	279	if (dm_gpio_get_value(desc)) {
	280	printf("\nReset u-boot environment (jumper)\n");
	281	run_command("run default_env; saveenv; saveenv", 0);
	282	}
	283	}
	284
f7cf76f8 HS	285	off = fdt_path_offset(gd->fdt_blob, "eeprom0");
	286	if (off < 0) {
	287	printf("%s: No eeprom0 path offset\n", __func__);
	288	return off;
	289	}
	290
	291	ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
	292	if (ret) {
	293	printf("%s: Could not find EEPROM\n", __func__);
	294	return ret;
	295	}
	296
	297	ret = i2c_set_chip_offset_len(dev, 2);
	298	if (ret)
	299	return ret;
	300
3cf02f5f	301	ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data));
f7cf76f8 HS	302	if (ret) {
	303	printf("%s: Could not read EEPROM\n", __func__);
	304	return ret;
	305	}
	306
3cf02f5f HS	307	/* software controlled reset of the environment (EEPROM magic) */
3cf02f5f HS	308	if (strncmp((char *)data, "DeF", 3) == 0) {
f7cf76f8 HS	309	memset(data, 0xff, 3);
f7cf76f8 HS	310	i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
3cf02f5f	311	printf("\nReset u-boot environment (EEPROM)\n");
f7cf76f8 HS	312	run_command("run default_env; saveenv; saveenv", 0);
	313	}
	314
3cf02f5f HS	315	if (sbmr1 & 0x40) {
	316	env_set("bootmode", "1");
	317	printf("SD bootmode jumper set!\n");
	318	} else {
	319	env_set("bootmode", "0");
	320	}
0f1130b6 HS	321
	322	/*
	323	* Check the boot-source. If booting from NOR Flash,
	324	* disable bootdelay
	325	*/
0ed133a6 HS	326	ret = gpio_hog_lookup_name("bootsel0", &desc);
0ed133a6 HS	327	if (!ret)
fc7e3cc6	328	bootmode \|= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
0ed133a6 HS	329	ret = gpio_hog_lookup_name("bootsel1", &desc);
0ed133a6 HS	330	if (!ret)
fc7e3cc6	331	bootmode \|= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
0ed133a6 HS	332	ret = gpio_hog_lookup_name("bootsel2", &desc);
0ed133a6 HS	333	if (!ret)
fc7e3cc6	334	bootmode \|= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
0f1130b6 HS	335
	336	if (bootmode == 7) {
	337	my_bootdelay = env_get("nor_bootdelay");
0ed133a6	338	if (my_bootdelay)
0f1130b6 HS	339	env_set("bootdelay", my_bootdelay);
	340	else
	341	env_set("bootdelay", "-2");
	342	}
	343
3cf02f5f	344	/* jumper controlled boot of the rescue system */
fc7e3cc6 HS	345	ret = gpio_hog_lookup_name("boot_rescue", &desc);
	346	if (!ret) {
	347	if (dm_gpio_get_value(desc)) {
3cf02f5f	348	printf("\nBooting into Rescue System (jumper)\n");
fc7e3cc6 HS	349	aristainetos_run_rescue_command(16);
	350	run_command("run rescue_xload_boot", 0);
	351	}
	352	}
3cf02f5f HS	353
	354	/* software controlled boot of the rescue system (EEPROM magic) */
	355	if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
	356	rescue_reason = (uint8_t )&data[9];
	357	memset(&data[3], 0xff, 7);
	358	i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
	359	printf("\nBooting into Rescue System (EEPROM)\n");
	360	aristainetos_run_rescue_command(rescue_reason);
	361	run_command("run rescue_xload_boot", 0);
	362	}
	363
	364	return 0;
0ed133a6 HS	365	}
0ed133a6 HS	366
158d93ad HS	367	#if defined(CONFIG_DM_PMIC_DA9063)
	368	/*
	369	* On the aristainetos2c boards the PMIC needs to be initialized,
	370	* because the Ethernet PHY uses a different regulator that is not
	371	* setup per hardware default. This does not influence the other versions
	372	* as this regulator isn't used there at all.
	373	*
	374	* Unfortunately we have not yet a interface to setup all
	375	* values we need.
	376	*/
	377	static int setup_pmic_voltages(void)
	378	{
	379	struct udevice *dev;
	380	int off;
	381	int ret;
	382
	383	off = fdt_path_offset(gd->fdt_blob, "pmic0");
	384	if (off < 0) {
	385	printf("%s: No pmic path offset\n", __func__);
	386	return off;
	387	}
	388
	389	ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
	390	if (ret) {
	391	printf("%s: Could not find PMIC\n", __func__);
	392	return ret;
	393	}
	394
	395	pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
	396	pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
	397	ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
	398	if (ret < 0) {
	399	printf("%s: error %d get register\n", __func__, ret);
	400	return ret;
	401	}
	402	ret &= 0xf0;
	403	ret \|= 0x09;
	404	pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
	405	pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
	406	pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
	407
	408	return 0;
	409	}
	410	#else
	411	static int setup_pmic_voltages(void)
	412	{
	413	return 0;
	414	}
	415	#endif
	416
0ed133a6 HS	417	int board_late_init(void)
	418	{
	419	int x, y;
3cf02f5f	420	int ret;
0ed133a6	421
0ed133a6 HS	422	splash_get_pos(&x, &y);
	423	bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
	424
3cf02f5f HS	425	ret = aristainetos_bootmode_settings();
	426	if (ret)
	427	return ret;
f7cf76f8	428
ccc7595a HS	429	/* set board_type */
	430	if (gd->board_type == BOARD_TYPE_4)
	431	env_set("board_type", ARI_BT_4);
	432	else
	433	env_set("board_type", ARI_BT_7);
0ed133a6	434
158d93ad HS	435	if (setup_pmic_voltages())
	436	printf("Error setup PMIC\n");
	437
0f1130b6 HS	438	return 0;
0f1130b6 HS	439	}
7254d92e	440
7254d92e	441	int dram_init(void)
e379c039	442	{
84c51687	443	gd->ram_size = imx_ddr_size();
e379c039	444
7254d92e	445	return 0;
e379c039 HS	446	}
e379c039 HS	447
e379c039 HS	448	struct display_info_t const displays[] = {
	449	{
	450	.bus = -1,
	451	.addr = 0,
	452	.pixfmt = IPU_PIX_FMT_RGB24,
	453	.detect = NULL,
	454	.enable = enable_lvds,
	455	.mode = {
	456	.name = "lb07wv8",
	457	.refresh = 60,
	458	.xres = 800,
	459	.yres = 480,
d0d005b6	460	.pixclock = 30066,
e379c039 HS	461	.left_margin = 88,
e379c039 HS	462	.right_margin = 88,
d0d005b6 HS	463	.upper_margin = 20,
d0d005b6 HS	464	.lower_margin = 20,
b4b39a7e	465	.hsync_len = 80,
d0d005b6 HS	466	.vsync_len = 5,
d0d005b6 HS	467	.sync = FB_SYNC_EXT,
e379c039 HS	468	.vmode = FB_VMODE_NONINTERLACED
	469	}
	470	}
	471	};
	472	size_t display_count = ARRAY_SIZE(displays);
	473
e379c039 HS	474	int board_init(void)
	475	{
	476	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	477
	478	/* address of boot parameters */
	479	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	480
7254d92e	481	setup_board_gpio();
621ff136	482	setup_display();
e379c039 HS	483
e379c039 HS	484	/* GPIO_1 for USB_OTG_ID */
7254d92e	485	clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
e379c039 HS	486	return 0;
	487	}
	488
ccc7595a HS	489	int board_fit_config_name_match(const char *name)
	490	{
	491	if (gd->board_type == BOARD_TYPE_4 &&
	492	strchr(name, 0x34))
	493	return 0;
	494
	495	if (gd->board_type == BOARD_TYPE_7 &&
	496	strchr(name, 0x37))
	497	return 0;
	498
	499	return -1;
	500	}
	501
	502	static void do_board_detect(void)
	503	{
	504	int ret;
	505	char s[30];
	506
	507	/* default use board type 7 */
	508	gd->board_type = BOARD_TYPE_7;
	509	if (env_init())
	510	return;
	511
	512	ret = env_get_f("panel", s, sizeof(s));
	513	if (ret < 0)
	514	return;
	515
	516	if (!strncmp("lg4573", s, 6))
	517	gd->board_type = BOARD_TYPE_4;
	518	}
	519
	520	#ifdef CONFIG_DTB_RESELECT
	521	int embedded_dtb_select(void)
	522	{
	523	int rescan;
	524
	525	do_board_detect();
	526	fdtdec_resetup(&rescan);
	527
e379c039 HS	528	return 0;
	529	}
	530	#endif