[people/ms/u-boot.git] / board / atmel / at91sam9261ek / at91sam9261ek.c

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <lcd.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#include <netdev.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
	unsigned long csa;

	/* Enable CS3 */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;

	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
#ifdef CONFIG_AT91SAM9G10EK
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
		&smc->cs[3].cycle);
#else
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);
#endif
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		       AT91_SMC_MODE_DBW_8 |
#endif
		       AT91_SMC_MODE_TDF_CYCLE(2),
		       &smc->cs[3].mode);

	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
}
#endif

#ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	/* Configure SMC CS2 for DM9000 */
#ifdef CONFIG_AT91SAM9G10EK
	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);
	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);
	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
		&smc->cs[2].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		       AT91_SMC_MODE_TDF_CYCLE(1),
		       &smc->cs[2].mode);
#else
	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);
	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
		&smc->cs[2].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		       AT91_SMC_MODE_TDF_CYCLE(1),
		       &smc->cs[2].mode);
#endif

	/* Configure Reset signal as output */
	at91_set_gpio_output(AT91_PIN_PC10, 0);

	/* Configure Interrupt pin as input, no pull-up */
	at91_set_gpio_input(AT91_PIN_PC11, 0);
}
#endif

#ifdef CONFIG_LCD
vidinfo_t panel_info = {
	.vl_col =		240,
	.vl_row =		320,
	.vl_clk =		4965000,
	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
				ATMEL_LCDC_INVFRAME_INVERTED,
	.vl_bpix =		3,
	.vl_tft =		1,
	.vl_hsync_len =		5,
	.vl_left_margin =	1,
	.vl_right_margin =	33,
	.vl_vsync_len =		1,
	.vl_upper_margin =	1,
	.vl_lower_margin =	0,
	.mmio =			ATMEL_BASE_LCDC,
};

void lcd_enable(void)
{
	at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
}

void lcd_disable(void)
{
	at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
}

static void at91sam9261ek_lcd_hw_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */

	writel(AT91_PMC_HCK1, &pmc->scer);

	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
#ifdef CONFIG_AT91SAM9261EK
	gd->fb_base = ATMEL_BASE_SRAM;
#endif
}

#ifdef CONFIG_LCD_INFO
#include <nand.h>
#include <version.h>

void lcd_show_board_info(void)
{
	ulong dram_size, nand_size;
	int i;
	char temp[32];

	lcd_printf ("%s\n", U_BOOT_VERSION);
	lcd_printf ("(C) 2008 ATMEL Corp\n");
	lcd_printf ("at91support@atmel.com\n");
	lcd_printf ("%s CPU at %s MHz\n",
		ATMEL_CPU_NAME,
		strmhz(temp, get_cpu_clk_rate()));

	dram_size = 0;
	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
		dram_size += gd->bd->bi_dram[i].size;
	nand_size = 0;
	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
		nand_size += nand_info[i].size;
	lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
		dram_size >> 20,
		nand_size >> 20 );
}
#endif /* CONFIG_LCD_INFO */
#endif

int board_init(void)
{
#ifdef CONFIG_AT91SAM9G10EK
	/* arch number of AT91SAM9G10EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
#else
	/* arch number of AT91SAM9261EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
#endif
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

	at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
	at91sam9261ek_nand_hw_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
	at91_spi0_hw_init(1 << 0);
#endif
#ifdef CONFIG_DRIVER_DM9000
	at91sam9261ek_dm9000_hw_init();
#endif
#ifdef CONFIG_LCD
	at91sam9261ek_lcd_hw_init();
#endif
	return 0;
}

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
	return dm9000_initialize(bis);
}
#endif

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
		CONFIG_SYS_SDRAM_SIZE);

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init(gd->bd);
#endif
}
#endif
Commit	Line	Data
d99a8ff6 SP	1	/*
d99a8ff6 SP	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
d99a8ff6 SP	4	* Lead Tech Design <www.leadtechdesign.com>
d99a8ff6 SP	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
d99a8ff6 SP	7	*/
	8
	9	#include <common.h>
f7aea46d	10	#include <asm/io.h>
d99a8ff6 SP	11	#include <asm/arch/at91sam9261.h>
	12	#include <asm/arch/at91sam9261_matrix.h>
	13	#include <asm/arch/at91sam9_smc.h>
1332a2a0	14	#include <asm/arch/at91_common.h>
d99a8ff6 SP	15	#include <asm/arch/at91_pmc.h>
d99a8ff6 SP	16	#include <asm/arch/at91_rstc.h>
dc39ae95	17	#include <asm/arch/clk.h>
d99a8ff6	18	#include <asm/arch/gpio.h>
820f2a95 SP	19	#include <lcd.h>
820f2a95 SP	20	#include <atmel_lcdc.h>
d99a8ff6 SP	21	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
d99a8ff6 SP	22	#include <net.h>
60f61e6d	23	#include <netdev.h>
d99a8ff6 SP	24	#endif
	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	/* ------------------------------------------------------------------------- */
	29	/*
	30	* Miscelaneous platform dependent initialisations
	31	*/
	32
d99a8ff6 SP	33	#ifdef CONFIG_CMD_NAND
	34	static void at91sam9261ek_nand_hw_init(void)
	35	{
f7aea46d XH	36	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
	37	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
	38	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
d99a8ff6 SP	39	unsigned long csa;
	40
	41	/* Enable CS3 */
f7aea46d XH	42	csa = readl(&matrix->ebicsa);
	43	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	44
	45	writel(csa, &matrix->ebicsa);
d99a8ff6 SP	46
d99a8ff6 SP	47	/* Configure SMC CS3 for NAND/SmartMedia */
5ccc2d99	48	#ifdef CONFIG_AT91SAM9G10EK
f7aea46d XH	49	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	50	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	51	&smc->cs[3].setup);
	52	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(7) \|
	53	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(7),
	54	&smc->cs[3].pulse);
	55	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(7),
	56	&smc->cs[3].cycle);
5ccc2d99	57	#else
f7aea46d XH	58	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	59	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	60	&smc->cs[3].setup);
	61	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	62	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	63	&smc->cs[3].pulse);
	64	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	65	&smc->cs[3].cycle);
5ccc2d99	66	#endif
f7aea46d XH	67	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
f7aea46d XH	68	AT91_SMC_MODE_EXNW_DISABLE \|
6d0f6bcf	69	#ifdef CONFIG_SYS_NAND_DBW_16
f7aea46d	70	AT91_SMC_MODE_DBW_16 \|
6d0f6bcf	71	#else /* CONFIG_SYS_NAND_DBW_8 */
f7aea46d	72	AT91_SMC_MODE_DBW_8 \|
d99a8ff6	73	#endif
f7aea46d XH	74	AT91_SMC_MODE_TDF_CYCLE(2),
f7aea46d XH	75	&smc->cs[3].mode);
d99a8ff6	76
f7aea46d	77	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
d99a8ff6 SP	78
d99a8ff6 SP	79	/* Configure RDY/BSY */
74c076d6	80	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
d99a8ff6 SP	81
d99a8ff6 SP	82	/* Enable NandFlash */
74c076d6	83	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
d99a8ff6 SP	84
	85	at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
	86	at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
	87	}
	88	#endif
	89
d99a8ff6 SP	90	#ifdef CONFIG_DRIVER_DM9000
	91	static void at91sam9261ek_dm9000_hw_init(void)
	92	{
f7aea46d XH	93	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f7aea46d XH	94
d99a8ff6	95	/* Configure SMC CS2 for DM9000 */
5ccc2d99	96	#ifdef CONFIG_AT91SAM9G10EK
f7aea46d XH	97	writel(AT91_SMC_SETUP_NWE(3) \| AT91_SMC_SETUP_NCS_WR(0) \|
	98	AT91_SMC_SETUP_NRD(3) \| AT91_SMC_SETUP_NCS_RD(0),
	99	&smc->cs[2].setup);
	100	writel(AT91_SMC_PULSE_NWE(6) \| AT91_SMC_PULSE_NCS_WR(8) \|
	101	AT91_SMC_PULSE_NRD(6) \| AT91_SMC_PULSE_NCS_RD(8),
	102	&smc->cs[2].pulse);
	103	writel(AT91_SMC_CYCLE_NWE(20) \| AT91_SMC_CYCLE_NRD(20),
	104	&smc->cs[2].cycle);
	105	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	106	AT91_SMC_MODE_EXNW_DISABLE \|
	107	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	108	AT91_SMC_MODE_TDF_CYCLE(1),
	109	&smc->cs[2].mode);
5ccc2d99	110	#else
f7aea46d XH	111	writel(AT91_SMC_SETUP_NWE(3) \| AT91_SMC_SETUP_NCS_WR(0) \|
	112	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	113	&smc->cs[2].setup);
	114	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(8) \|
	115	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(8),
	116	&smc->cs[2].pulse);
	117	writel(AT91_SMC_CYCLE_NWE(16) \| AT91_SMC_CYCLE_NRD(16),
	118	&smc->cs[2].cycle);
	119	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	120	AT91_SMC_MODE_EXNW_DISABLE \|
	121	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	122	AT91_SMC_MODE_TDF_CYCLE(1),
	123	&smc->cs[2].mode);
5ccc2d99	124	#endif
d99a8ff6 SP	125
	126	/* Configure Reset signal as output */
	127	at91_set_gpio_output(AT91_PIN_PC10, 0);
	128
	129	/* Configure Interrupt pin as input, no pull-up */
	130	at91_set_gpio_input(AT91_PIN_PC11, 0);
	131	}
	132	#endif
	133
820f2a95 SP	134	#ifdef CONFIG_LCD
820f2a95 SP	135	vidinfo_t panel_info = {
c346e466 JH	136	.vl_col = 240,
	137	.vl_row = 320,
	138	.vl_clk = 4965000,
	139	.vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	140	ATMEL_LCDC_INVFRAME_INVERTED,
	141	.vl_bpix = 3,
	142	.vl_tft = 1,
	143	.vl_hsync_len = 5,
	144	.vl_left_margin = 1,
	145	.vl_right_margin = 33,
	146	.vl_vsync_len = 1,
	147	.vl_upper_margin = 1,
	148	.vl_lower_margin = 0,
	149	.mmio = ATMEL_BASE_LCDC,
820f2a95 SP	150	};
	151
	152	void lcd_enable(void)
	153	{
	154	at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
	155	}
	156
	157	void lcd_disable(void)
	158	{
	159	at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
	160	}
	161
	162	static void at91sam9261ek_lcd_hw_init(void)
	163	{
f7aea46d XH	164	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
f7aea46d XH	165
820f2a95 SP	166	at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
	167	at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
	168	at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
	169	at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
	170	at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
	171	at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
	172	at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
	173	at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
	174	at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
	175	at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
	176	at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
	177	at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
	178	at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
	179	at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
	180	at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
	181	at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
	182	at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
	183	at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
	184	at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
	185	at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
	186	at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
	187	at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
	188
f7aea46d	189	writel(AT91_PMC_HCK1, &pmc->scer);
820f2a95	190
f7aea46d XH	191	/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
	192	#ifdef CONFIG_AT91SAM9261EK
	193	gd->fb_base = ATMEL_BASE_SRAM;
5ccc2d99	194	#endif
820f2a95	195	}
6b59e03e HS	196
	197	#ifdef CONFIG_LCD_INFO
	198	#include <nand.h>
	199	#include <version.h>
	200
	201	void lcd_show_board_info(void)
	202	{
	203	ulong dram_size, nand_size;
	204	int i;
	205	char temp[32];
	206
	207	lcd_printf ("%s\n", U_BOOT_VERSION);
	208	lcd_printf ("(C) 2008 ATMEL Corp\n");
	209	lcd_printf ("at91support@atmel.com\n");
	210	lcd_printf ("%s CPU at %s MHz\n",
f7aea46d	211	ATMEL_CPU_NAME,
dc39ae95	212	strmhz(temp, get_cpu_clk_rate()));
6b59e03e HS	213
	214	dram_size = 0;
	215	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	216	dram_size += gd->bd->bi_dram[i].size;
	217	nand_size = 0;
	218	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	219	nand_size += nand_info[i].size;
	220	lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
	221	dram_size >> 20,
	222	nand_size >> 20 );
	223	}
	224	#endif /* CONFIG_LCD_INFO */
820f2a95 SP	225	#endif
820f2a95 SP	226
d99a8ff6 SP	227	int board_init(void)
d99a8ff6 SP	228	{
5ccc2d99 SG	229	#ifdef CONFIG_AT91SAM9G10EK
	230	/* arch number of AT91SAM9G10EK-Board */
	231	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
	232	#else
d99a8ff6 SP	233	/* arch number of AT91SAM9261EK-Board */
d99a8ff6 SP	234	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
5ccc2d99	235	#endif
d99a8ff6	236	/* adress of boot parameters */
f7aea46d	237	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
d99a8ff6	238
f7aea46d	239	at91_seriald_hw_init();
d99a8ff6 SP	240	#ifdef CONFIG_CMD_NAND
	241	at91sam9261ek_nand_hw_init();
	242	#endif
	243	#ifdef CONFIG_HAS_DATAFLASH
7ebafb7e	244	at91_spi0_hw_init(1 << 0);
d99a8ff6 SP	245	#endif
	246	#ifdef CONFIG_DRIVER_DM9000
	247	at91sam9261ek_dm9000_hw_init();
820f2a95 SP	248	#endif
	249	#ifdef CONFIG_LCD
	250	at91sam9261ek_lcd_hw_init();
d99a8ff6 SP	251	#endif
	252	return 0;
	253	}
	254
60f61e6d	255	#ifdef CONFIG_DRIVER_DM9000
e8fac25e WD	256	int board_eth_init(bd_t *bis)
e8fac25e WD	257	{
60f61e6d	258	return dm9000_initialize(bis);
e8fac25e WD	259	}
	260	#endif
	261
d99a8ff6 SP	262	int dram_init(void)
d99a8ff6 SP	263	{
f7aea46d XH	264	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
	265	CONFIG_SYS_SDRAM_SIZE);
	266
d99a8ff6 SP	267	return 0;
	268	}
	269
	270	#ifdef CONFIG_RESET_PHY_R
	271	void reset_phy(void)
	272	{
	273	#ifdef CONFIG_DRIVER_DM9000
	274	/*
	275	* Initialize ethernet HW addr prior to starting Linux,
	276	* needed for nfsroot
	277	*/
	278	eth_init(gd->bd);
	279	#endif
	280	}
	281	#endif