[thirdparty/u-boot.git] / board / atmel / at91sam9261ek / at91sam9261ek.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 */

#include <common.h>
#include <debug_uart.h>
#include <init.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/at91sam9261.h>
#include <asm/arch/at91sam9261_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
#include <net.h>
#include <netdev.h>
#endif
#include <asm/mach-types.h>

DECLARE_GLOBAL_DATA_PTR;

/* ------------------------------------------------------------------------- */
/*
 * Miscelaneous platform dependent initialisations
 */

#ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
	unsigned long csa;

	/* Enable CS3 */
	csa = readl(&matrix->ebicsa);
	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;

	writel(csa, &matrix->ebicsa);

	/* Configure SMC CS3 for NAND/SmartMedia */
#ifdef CONFIG_AT91SAM9G10EK
	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
		&smc->cs[3].cycle);
#else
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[3].setup);
	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
		&smc->cs[3].pulse);
	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
		&smc->cs[3].cycle);
#endif
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
		       AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
		       AT91_SMC_MODE_DBW_8 |
#endif
		       AT91_SMC_MODE_TDF_CYCLE(2),
		       &smc->cs[3].mode);

	at91_periph_clk_enable(ATMEL_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);

	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
}
#endif

#ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init(void)
{
	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	/* Configure SMC CS2 for DM9000 */
#ifdef CONFIG_AT91SAM9G10EK
	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);
	writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);
	writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
		&smc->cs[2].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		       AT91_SMC_MODE_TDF_CYCLE(1),
		       &smc->cs[2].mode);
#else
	writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
		&smc->cs[2].setup);
	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
		AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
		&smc->cs[2].pulse);
	writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
		&smc->cs[2].cycle);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
		       AT91_SMC_MODE_EXNW_DISABLE |
		       AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
		       AT91_SMC_MODE_TDF_CYCLE(1),
		       &smc->cs[2].mode);
#endif

	/* Configure Reset signal as output */
	at91_set_gpio_output(AT91_PIN_PC10, 0);

	/* Configure Interrupt pin as input, no pull-up */
	at91_set_gpio_input(AT91_PIN_PC11, 0);
}
#endif

#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
	at91_seriald_hw_init();
}
#endif

#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
	return 0;
}
#endif

int board_init(void)
{
#ifdef CONFIG_AT91SAM9G10EK
	/* arch number of AT91SAM9G10EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
#else
	/* arch number of AT91SAM9261EK-Board */
	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
#endif
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

#ifdef CONFIG_CMD_NAND
	at91sam9261ek_nand_hw_init();
#endif
#ifdef CONFIG_DRIVER_DM9000
	at91sam9261ek_dm9000_hw_init();
#endif
	return 0;
}

#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(struct bd_info *bis)
{
	return dm9000_initialize(bis);
}
#endif

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
		CFG_SYS_SDRAM_SIZE);

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_DRIVER_DM9000
	/*
	 * Initialize ethernet HW addr prior to starting Linux,
	 * needed for nfsroot
	 */
	eth_init();
#endif
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
d99a8ff6 SP	2	/*
d99a8ff6 SP	3	* (C) Copyright 2007-2008
c9e798d3	4	* Stelian Pop <stelian@popies.net>
d99a8ff6	5	* Lead Tech Design <www.leadtechdesign.com>
d99a8ff6 SP	6	*/
d99a8ff6 SP	7
d678a59d	8	#include <common.h>
324873e7	9	#include <debug_uart.h>
9b4a205f	10	#include <init.h>
2189d5f1	11	#include <vsprintf.h>
401d1c4f	12	#include <asm/global_data.h>
f7aea46d	13	#include <asm/io.h>
d99a8ff6 SP	14	#include <asm/arch/at91sam9261.h>
	15	#include <asm/arch/at91sam9261_matrix.h>
	16	#include <asm/arch/at91sam9_smc.h>
1332a2a0	17	#include <asm/arch/at91_common.h>
d99a8ff6	18	#include <asm/arch/at91_rstc.h>
dc39ae95	19	#include <asm/arch/clk.h>
d99a8ff6	20	#include <asm/arch/gpio.h>
820f2a95	21	#include <atmel_lcdc.h>
d99a8ff6 SP	22	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
d99a8ff6 SP	23	#include <net.h>
60f61e6d	24	#include <netdev.h>
d99a8ff6	25	#endif
c62db35d	26	#include <asm/mach-types.h>
d99a8ff6 SP	27
	28	DECLARE_GLOBAL_DATA_PTR;
	29
	30	/* ------------------------------------------------------------------------- */
	31	/*
	32	* Miscelaneous platform dependent initialisations
	33	*/
	34
d99a8ff6 SP	35	#ifdef CONFIG_CMD_NAND
	36	static void at91sam9261ek_nand_hw_init(void)
	37	{
f7aea46d XH	38	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f7aea46d XH	39	struct at91_matrix matrix = (struct at91_matrix )ATMEL_BASE_MATRIX;
d99a8ff6 SP	40	unsigned long csa;
	41
	42	/* Enable CS3 */
f7aea46d XH	43	csa = readl(&matrix->ebicsa);
	44	csa \|= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
	45
	46	writel(csa, &matrix->ebicsa);
d99a8ff6 SP	47
d99a8ff6 SP	48	/* Configure SMC CS3 for NAND/SmartMedia */
5ccc2d99	49	#ifdef CONFIG_AT91SAM9G10EK
f7aea46d XH	50	writel(AT91_SMC_SETUP_NWE(2) \| AT91_SMC_SETUP_NCS_WR(0) \|
	51	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	52	&smc->cs[3].setup);
	53	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(7) \|
	54	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(7),
	55	&smc->cs[3].pulse);
	56	writel(AT91_SMC_CYCLE_NWE(7) \| AT91_SMC_CYCLE_NRD(7),
	57	&smc->cs[3].cycle);
5ccc2d99	58	#else
f7aea46d XH	59	writel(AT91_SMC_SETUP_NWE(1) \| AT91_SMC_SETUP_NCS_WR(0) \|
	60	AT91_SMC_SETUP_NRD(1) \| AT91_SMC_SETUP_NCS_RD(0),
	61	&smc->cs[3].setup);
	62	writel(AT91_SMC_PULSE_NWE(3) \| AT91_SMC_PULSE_NCS_WR(3) \|
	63	AT91_SMC_PULSE_NRD(3) \| AT91_SMC_PULSE_NCS_RD(3),
	64	&smc->cs[3].pulse);
	65	writel(AT91_SMC_CYCLE_NWE(5) \| AT91_SMC_CYCLE_NRD(5),
	66	&smc->cs[3].cycle);
5ccc2d99	67	#endif
f7aea46d XH	68	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
f7aea46d XH	69	AT91_SMC_MODE_EXNW_DISABLE \|
6d0f6bcf	70	#ifdef CONFIG_SYS_NAND_DBW_16
f7aea46d	71	AT91_SMC_MODE_DBW_16 \|
6d0f6bcf	72	#else /* CONFIG_SYS_NAND_DBW_8 */
f7aea46d	73	AT91_SMC_MODE_DBW_8 \|
d99a8ff6	74	#endif
f7aea46d XH	75	AT91_SMC_MODE_TDF_CYCLE(2),
f7aea46d XH	76	&smc->cs[3].mode);
d99a8ff6	77
70341e2e	78	at91_periph_clk_enable(ATMEL_ID_PIOC);
d99a8ff6 SP	79
d99a8ff6 SP	80	/* Configure RDY/BSY */
4e590945	81	at91_set_gpio_input(CFG_SYS_NAND_READY_PIN, 1);
d99a8ff6 SP	82
d99a8ff6 SP	83	/* Enable NandFlash */
4e590945	84	at91_set_gpio_output(CFG_SYS_NAND_ENABLE_PIN, 1);
d99a8ff6 SP	85
	86	at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
	87	at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
	88	}
	89	#endif
	90
d99a8ff6 SP	91	#ifdef CONFIG_DRIVER_DM9000
	92	static void at91sam9261ek_dm9000_hw_init(void)
	93	{
f7aea46d XH	94	struct at91_smc smc = (struct at91_smc )ATMEL_BASE_SMC;
f7aea46d XH	95
d99a8ff6	96	/* Configure SMC CS2 for DM9000 */
5ccc2d99	97	#ifdef CONFIG_AT91SAM9G10EK
f7aea46d XH	98	writel(AT91_SMC_SETUP_NWE(3) \| AT91_SMC_SETUP_NCS_WR(0) \|
	99	AT91_SMC_SETUP_NRD(3) \| AT91_SMC_SETUP_NCS_RD(0),
	100	&smc->cs[2].setup);
	101	writel(AT91_SMC_PULSE_NWE(6) \| AT91_SMC_PULSE_NCS_WR(8) \|
	102	AT91_SMC_PULSE_NRD(6) \| AT91_SMC_PULSE_NCS_RD(8),
	103	&smc->cs[2].pulse);
	104	writel(AT91_SMC_CYCLE_NWE(20) \| AT91_SMC_CYCLE_NRD(20),
	105	&smc->cs[2].cycle);
	106	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	107	AT91_SMC_MODE_EXNW_DISABLE \|
	108	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	109	AT91_SMC_MODE_TDF_CYCLE(1),
	110	&smc->cs[2].mode);
5ccc2d99	111	#else
f7aea46d XH	112	writel(AT91_SMC_SETUP_NWE(3) \| AT91_SMC_SETUP_NCS_WR(0) \|
	113	AT91_SMC_SETUP_NRD(2) \| AT91_SMC_SETUP_NCS_RD(0),
	114	&smc->cs[2].setup);
	115	writel(AT91_SMC_PULSE_NWE(4) \| AT91_SMC_PULSE_NCS_WR(8) \|
	116	AT91_SMC_PULSE_NRD(4) \| AT91_SMC_PULSE_NCS_RD(8),
	117	&smc->cs[2].pulse);
	118	writel(AT91_SMC_CYCLE_NWE(16) \| AT91_SMC_CYCLE_NRD(16),
	119	&smc->cs[2].cycle);
	120	writel(AT91_SMC_MODE_RM_NRD \| AT91_SMC_MODE_WM_NWE \|
	121	AT91_SMC_MODE_EXNW_DISABLE \|
	122	AT91_SMC_MODE_BAT \| AT91_SMC_MODE_DBW_16 \|
	123	AT91_SMC_MODE_TDF_CYCLE(1),
	124	&smc->cs[2].mode);
5ccc2d99	125	#endif
d99a8ff6 SP	126
	127	/* Configure Reset signal as output */
	128	at91_set_gpio_output(AT91_PIN_PC10, 0);
	129
	130	/* Configure Interrupt pin as input, no pull-up */
	131	at91_set_gpio_input(AT91_PIN_PC11, 0);
	132	}
	133	#endif
	134
324873e7 WY	135	#ifdef CONFIG_DEBUG_UART_BOARD_INIT
	136	void board_debug_uart_init(void)
	137	{
	138	at91_seriald_hw_init();
	139	}
	140	#endif
	141
	142	#ifdef CONFIG_BOARD_EARLY_INIT_F
	143	int board_early_init_f(void)
	144	{
324873e7 WY	145	return 0;
	146	}
	147	#endif
	148
d99a8ff6 SP	149	int board_init(void)
d99a8ff6 SP	150	{
5ccc2d99 SG	151	#ifdef CONFIG_AT91SAM9G10EK
	152	/* arch number of AT91SAM9G10EK-Board */
	153	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
	154	#else
d99a8ff6 SP	155	/* arch number of AT91SAM9261EK-Board */
d99a8ff6 SP	156	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
5ccc2d99	157	#endif
d99a8ff6	158	/* adress of boot parameters */
aa6e94de	159	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
d99a8ff6	160
d99a8ff6 SP	161	#ifdef CONFIG_CMD_NAND
	162	at91sam9261ek_nand_hw_init();
	163	#endif
d99a8ff6 SP	164	#ifdef CONFIG_DRIVER_DM9000
	165	at91sam9261ek_dm9000_hw_init();
	166	#endif
	167	return 0;
	168	}
	169
60f61e6d	170	#ifdef CONFIG_DRIVER_DM9000
b75d8dc5	171	int board_eth_init(struct bd_info *bis)
e8fac25e	172	{
60f61e6d	173	return dm9000_initialize(bis);
e8fac25e WD	174	}
	175	#endif
	176
d99a8ff6 SP	177	int dram_init(void)
d99a8ff6 SP	178	{
aa6e94de TR	179	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
aa6e94de TR	180	CFG_SYS_SDRAM_SIZE);
f7aea46d	181
d99a8ff6 SP	182	return 0;
	183	}
	184
	185	#ifdef CONFIG_RESET_PHY_R
	186	void reset_phy(void)
	187	{
	188	#ifdef CONFIG_DRIVER_DM9000
	189	/*
	190	* Initialize ethernet HW addr prior to starting Linux,
	191	* needed for nfsroot
	192	*/
d2eaec60	193	eth_init();
d99a8ff6 SP	194	#endif
	195	}
	196	#endif