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1 | /* |
2 | * (C) Copyright 2007-2008 | |
3 | * Stelian Pop <stelian.pop@leadtechdesign.com> | |
4 | * Lead Tech Design <www.leadtechdesign.com> | |
5 | * | |
6 | * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <asm/arch/at91sam9263.h> | |
29 | #include <asm/arch/gpio.h> | |
30 | #include <asm/arch/at91_pio.h> | |
31 | ||
32 | #include <nand.h> | |
33 | ||
34 | /* | |
35 | * hardware specific access to control-lines | |
36 | */ | |
37 | #define MASK_ALE (1 << 21) /* our ALE is AD21 */ | |
38 | #define MASK_CLE (1 << 22) /* our CLE is AD22 */ | |
39 | ||
aa5f75f2 SW |
40 | static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, |
41 | int cmd, unsigned int ctrl) | |
8e429b3e SP |
42 | { |
43 | struct nand_chip *this = mtd->priv; | |
8e429b3e | 44 | |
aa5f75f2 SW |
45 | if (ctrl & NAND_CTRL_CHANGE) { |
46 | ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; | |
47 | IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); | |
48 | ||
49 | if (ctrl & NAND_CLE) | |
50 | IO_ADDR_W |= MASK_CLE; | |
51 | if (ctrl & NAND_ALE) | |
52 | IO_ADDR_W |= MASK_ALE; | |
53 | ||
54 | at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); | |
55 | this->IO_ADDR_W = (void *) IO_ADDR_W; | |
8e429b3e | 56 | } |
aa5f75f2 SW |
57 | |
58 | if (cmd != NAND_CMD_NONE) | |
59 | writeb(cmd, this->IO_ADDR_W); | |
8e429b3e SP |
60 | } |
61 | ||
62 | static int at91sam9263ek_nand_ready(struct mtd_info *mtd) | |
63 | { | |
64 | return at91_get_gpio_value(AT91_PIN_PA22); | |
65 | } | |
66 | ||
67 | int board_nand_init(struct nand_chip *nand) | |
68 | { | |
aa5f75f2 | 69 | nand->ecc.mode = NAND_ECC_SOFT; |
6d0f6bcf | 70 | #ifdef CONFIG_SYS_NAND_DBW_16 |
8e429b3e SP |
71 | nand->options = NAND_BUSWIDTH_16; |
72 | #endif | |
aa5f75f2 | 73 | nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol; |
8e429b3e SP |
74 | nand->dev_ready = at91sam9263ek_nand_ready; |
75 | nand->chip_delay = 20; | |
76 | ||
77 | return 0; | |
78 | } |