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9e336903 WJ |
1 | /* |
2 | * (C) Copyright 2013 Atmel Corporation | |
3 | * Josh Wu <josh.wu@atmel.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
9e336903 WJ |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/arch/at91sam9x5_matrix.h> | |
11 | #include <asm/arch/at91sam9_smc.h> | |
12 | #include <asm/arch/at91_common.h> | |
13 | #include <asm/arch/at91_pmc.h> | |
14 | #include <asm/arch/at91_rstc.h> | |
15 | #include <asm/arch/at91_pio.h> | |
16 | #include <asm/arch/clk.h> | |
17 | #include <lcd.h> | |
18 | #include <atmel_hlcdc.h> | |
19 | #include <atmel_mci.h> | |
16276220 | 20 | #include <netdev.h> |
9e336903 WJ |
21 | |
22 | #ifdef CONFIG_LCD_INFO | |
23 | #include <nand.h> | |
24 | #include <version.h> | |
25 | #endif | |
26 | ||
27 | DECLARE_GLOBAL_DATA_PTR; | |
28 | ||
29 | /* ------------------------------------------------------------------------- */ | |
30 | /* | |
31 | * Miscelaneous platform dependent initialisations | |
32 | */ | |
33 | #ifdef CONFIG_NAND_ATMEL | |
34 | static void at91sam9n12ek_nand_hw_init(void) | |
35 | { | |
36 | struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; | |
37 | struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; | |
38 | unsigned long csa; | |
39 | ||
40 | /* Assign CS3 to NAND/SmartMedia Interface */ | |
41 | csa = readl(&matrix->ebicsa); | |
42 | csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; | |
43 | /* Configure databus */ | |
44 | csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */ | |
45 | /* Configure IO drive */ | |
b899fa39 | 46 | csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL; |
9e336903 WJ |
47 | |
48 | writel(csa, &matrix->ebicsa); | |
49 | ||
50 | /* Configure SMC CS3 for NAND/SmartMedia */ | |
51 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | | |
52 | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), | |
53 | &smc->cs[3].setup); | |
54 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) | | |
55 | AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6), | |
56 | &smc->cs[3].pulse); | |
57 | writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7), | |
58 | &smc->cs[3].cycle); | |
59 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
60 | AT91_SMC_MODE_EXNW_DISABLE | | |
61 | #ifdef CONFIG_SYS_NAND_DBW_16 | |
62 | AT91_SMC_MODE_DBW_16 | | |
63 | #else /* CONFIG_SYS_NAND_DBW_8 */ | |
64 | AT91_SMC_MODE_DBW_8 | | |
65 | #endif | |
66 | AT91_SMC_MODE_TDF_CYCLE(1), | |
67 | &smc->cs[3].mode); | |
68 | ||
69 | /* Configure RDY/BSY pin */ | |
70 | at91_set_pio_input(AT91_PIO_PORTD, 5, 1); | |
71 | ||
72 | /* Configure ENABLE pin for NandFlash */ | |
73 | at91_set_pio_output(AT91_PIO_PORTD, 4, 1); | |
74 | ||
75 | at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ | |
76 | at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ | |
77 | at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */ | |
78 | at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */ | |
79 | } | |
80 | #endif | |
81 | ||
82 | #ifdef CONFIG_LCD | |
83 | vidinfo_t panel_info = { | |
84 | .vl_col = 480, | |
85 | .vl_row = 272, | |
86 | .vl_clk = 9000000, | |
87 | .vl_bpix = LCD_BPP, | |
88 | .vl_sync = 0, | |
89 | .vl_tft = 1, | |
90 | .vl_hsync_len = 5, | |
91 | .vl_left_margin = 8, | |
92 | .vl_right_margin = 43, | |
93 | .vl_vsync_len = 10, | |
94 | .vl_upper_margin = 4, | |
95 | .vl_lower_margin = 12, | |
96 | .mmio = ATMEL_BASE_LCDC, | |
97 | }; | |
98 | ||
99 | void lcd_enable(void) | |
100 | { | |
101 | at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */ | |
102 | } | |
103 | ||
104 | void lcd_disable(void) | |
105 | { | |
106 | at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */ | |
107 | } | |
108 | ||
109 | #ifdef CONFIG_LCD_INFO | |
110 | void lcd_show_board_info(void) | |
111 | { | |
112 | ulong dram_size, nand_size; | |
113 | int i; | |
114 | char temp[32]; | |
115 | ||
116 | lcd_printf("%s\n", U_BOOT_VERSION); | |
117 | lcd_printf("ATMEL Corp\n"); | |
118 | lcd_printf("at91@atmel.com\n"); | |
119 | lcd_printf("%s CPU at %s MHz\n", | |
120 | ATMEL_CPU_NAME, | |
121 | strmhz(temp, get_cpu_clk_rate())); | |
122 | ||
123 | dram_size = 0; | |
124 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) | |
125 | dram_size += gd->bd->bi_dram[i].size; | |
126 | nand_size = 0; | |
127 | for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) | |
128 | nand_size += nand_info[i].size; | |
129 | lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", | |
130 | dram_size >> 20, | |
131 | nand_size >> 20); | |
132 | } | |
133 | #endif /* CONFIG_LCD_INFO */ | |
134 | #endif /* CONFIG_LCD */ | |
135 | ||
136 | /* SPI chip select control */ | |
137 | #ifdef CONFIG_ATMEL_SPI | |
138 | #include <spi.h> | |
139 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
140 | { | |
141 | return bus == 0 && cs < 2; | |
142 | } | |
143 | ||
144 | void spi_cs_activate(struct spi_slave *slave) | |
145 | { | |
146 | switch (slave->cs) { | |
147 | case 0: | |
148 | at91_set_pio_output(AT91_PIO_PORTA, 14, 0); | |
149 | break; | |
150 | case 1: | |
151 | at91_set_pio_output(AT91_PIO_PORTA, 7, 0); | |
152 | break; | |
153 | } | |
154 | } | |
155 | ||
156 | void spi_cs_deactivate(struct spi_slave *slave) | |
157 | { | |
158 | switch (slave->cs) { | |
159 | case 0: | |
160 | at91_set_pio_output(AT91_PIO_PORTA, 14, 1); | |
161 | break; | |
162 | case 1: | |
163 | at91_set_pio_output(AT91_PIO_PORTA, 7, 1); | |
164 | break; | |
165 | } | |
166 | } | |
167 | #endif /* CONFIG_ATMEL_SPI */ | |
168 | ||
169 | #ifdef CONFIG_GENERIC_ATMEL_MCI | |
170 | int board_mmc_init(bd_t *bd) | |
171 | { | |
172 | at91_mci_hw_init(); | |
173 | ||
174 | return atmel_mci_init((void *)ATMEL_BASE_HSMCI0); | |
175 | } | |
176 | #endif | |
177 | ||
16276220 BS |
178 | #ifdef CONFIG_KS8851_MLL |
179 | void at91sam9n12ek_ks8851_hw_init(void) | |
180 | { | |
181 | struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; | |
182 | ||
183 | writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | | |
184 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), | |
185 | &smc->cs[2].setup); | |
186 | writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) | | |
187 | AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7), | |
188 | &smc->cs[2].pulse); | |
189 | writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9), | |
190 | &smc->cs[2].cycle); | |
191 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
192 | AT91_SMC_MODE_EXNW_DISABLE | | |
193 | AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 | | |
194 | AT91_SMC_MODE_TDF_CYCLE(1), | |
195 | &smc->cs[2].mode); | |
196 | ||
197 | /* Configure NCS2 PIN */ | |
198 | at91_set_b_periph(AT91_PIO_PORTD, 19, 0); | |
199 | } | |
200 | #endif | |
201 | ||
9e336903 WJ |
202 | int board_early_init_f(void) |
203 | { | |
204 | /* Enable clocks for all PIOs */ | |
205 | struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; | |
206 | writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer); | |
207 | ||
208 | at91_seriald_hw_init(); | |
209 | return 0; | |
210 | } | |
211 | ||
212 | int board_init(void) | |
213 | { | |
214 | /* adress of boot parameters */ | |
215 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | |
216 | ||
217 | #ifdef CONFIG_NAND_ATMEL | |
218 | at91sam9n12ek_nand_hw_init(); | |
219 | #endif | |
220 | ||
221 | #ifdef CONFIG_ATMEL_SPI | |
222 | at91_spi0_hw_init(1 << 0); | |
223 | #endif | |
224 | ||
225 | #ifdef CONFIG_LCD | |
226 | at91_lcd_hw_init(); | |
227 | #endif | |
228 | ||
16276220 BS |
229 | #ifdef CONFIG_KS8851_MLL |
230 | at91sam9n12ek_ks8851_hw_init(); | |
231 | #endif | |
232 | ||
9e336903 WJ |
233 | return 0; |
234 | } | |
235 | ||
16276220 BS |
236 | #ifdef CONFIG_KS8851_MLL |
237 | int board_eth_init(bd_t *bis) | |
238 | { | |
239 | return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR); | |
240 | } | |
241 | #endif | |
242 | ||
9e336903 WJ |
243 | int dram_init(void) |
244 | { | |
245 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, | |
246 | CONFIG_SYS_SDRAM_SIZE); | |
247 | return 0; | |
248 | } |