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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ce4054bf WY |
2 | /* |
3 | * Copyright (C) 2017 Microchip Corporation | |
4 | * Wenyou.Yang <wenyou.yang@microchip.com> | |
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5 | */ |
6 | ||
d678a59d | 7 | #include <common.h> |
ce4054bf | 8 | #include <debug_uart.h> |
73c1589f | 9 | #include <fdtdec.h> |
5255932f | 10 | #include <init.h> |
401d1c4f | 11 | #include <asm/global_data.h> |
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12 | #include <asm/io.h> |
13 | #include <asm/arch/at91_common.h> | |
14 | #include <asm/arch/atmel_pio4.h> | |
15 | #include <asm/arch/atmel_mpddrc.h> | |
16 | #include <asm/arch/atmel_sdhci.h> | |
17 | #include <asm/arch/clk.h> | |
18 | #include <asm/arch/gpio.h> | |
19 | #include <asm/arch/sama5d2.h> | |
20 | ||
67f551af EH |
21 | extern void at91_pda_detect(void); |
22 | ||
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23 | DECLARE_GLOBAL_DATA_PTR; |
24 | ||
d05fc47b MS |
25 | static void rgb_leds_init(void) |
26 | { | |
27 | atmel_pio4_set_pio_output(AT91_PIO_PORTA, 10, 0); /* LED RED */ | |
28 | atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0); /* LED GREEN */ | |
29 | atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1); /* LED BLUE */ | |
30 | } | |
31 | ||
ef5a7438 | 32 | #ifdef CONFIG_CMD_USB |
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33 | static void board_usb_hw_init(void) |
34 | { | |
528a42a7 | 35 | atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1); |
ce4054bf | 36 | } |
ef5a7438 | 37 | #endif |
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38 | |
39 | #ifdef CONFIG_BOARD_LATE_INIT | |
40 | int board_late_init(void) | |
41 | { | |
b86986c7 | 42 | #ifdef CONFIG_VIDEO |
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43 | at91_video_show_board_info(); |
44 | #endif | |
67f551af | 45 | at91_pda_detect(); |
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46 | return 0; |
47 | } | |
48 | #endif | |
49 | ||
50 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT | |
51 | static void board_uart1_hw_init(void) | |
52 | { | |
8ee54672 | 53 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */ |
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54 | atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */ |
55 | ||
56 | at91_periph_clk_enable(ATMEL_ID_UART1); | |
57 | } | |
58 | ||
59 | void board_debug_uart_init(void) | |
60 | { | |
61 | board_uart1_hw_init(); | |
62 | } | |
63 | #endif | |
64 | ||
65 | #ifdef CONFIG_BOARD_EARLY_INIT_F | |
66 | int board_early_init_f(void) | |
67 | { | |
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68 | return 0; |
69 | } | |
70 | #endif | |
71 | ||
72 | int board_init(void) | |
73 | { | |
74 | /* address of boot parameters */ | |
73c1589f | 75 | gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; |
ce4054bf | 76 | |
d05fc47b MS |
77 | rgb_leds_init(); |
78 | ||
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79 | #ifdef CONFIG_CMD_USB |
80 | board_usb_hw_init(); | |
81 | #endif | |
82 | ||
83 | return 0; | |
84 | } | |
85 | ||
73c1589f CL |
86 | int dram_init_banksize(void) |
87 | { | |
88 | return fdtdec_setup_memory_banksize(); | |
89 | } | |
90 | ||
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91 | int dram_init(void) |
92 | { | |
73c1589f | 93 | return fdtdec_setup_mem_size_base(); |
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94 | } |
95 | ||
96 | #define MAC24AA_MAC_OFFSET 0xfa | |
97 | ||
98 | #ifdef CONFIG_MISC_INIT_R | |
99 | int misc_init_r(void) | |
100 | { | |
101 | #ifdef CONFIG_I2C_EEPROM | |
102 | at91_set_ethaddr(MAC24AA_MAC_OFFSET); | |
103 | #endif | |
104 | return 0; | |
105 | } | |
106 | #endif | |
107 | ||
108 | /* SPL */ | |
109 | #ifdef CONFIG_SPL_BUILD | |
110 | void spl_board_init(void) | |
111 | { | |
112 | } | |
113 | ||
114 | static void ddrc_conf(struct atmel_mpddrc_config *ddrc) | |
115 | { | |
116 | ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); | |
117 | ||
118 | ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | | |
119 | ATMEL_MPDDRC_CR_NR_ROW_13 | | |
120 | ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | | |
121 | ATMEL_MPDDRC_CR_DIC_DS | | |
122 | ATMEL_MPDDRC_CR_ZQ_LONG | | |
123 | ATMEL_MPDDRC_CR_NB_8BANKS | | |
124 | ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | | |
125 | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); | |
126 | ||
127 | ddrc->rtr = 0x511; | |
128 | ||
129 | ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | | |
130 | (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | | |
131 | (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | | |
132 | (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | | |
133 | (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | | |
134 | (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | | |
135 | (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | | |
136 | (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); | |
137 | ||
138 | ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | | |
139 | (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | | |
140 | (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | | |
141 | (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); | |
142 | ||
143 | ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | | |
144 | (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | | |
145 | (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | | |
146 | (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | | |
147 | (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); | |
148 | } | |
149 | ||
150 | void mem_init(void) | |
151 | { | |
152 | struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; | |
153 | struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; | |
154 | struct atmel_mpddrc_config ddrc_config; | |
155 | u32 reg; | |
156 | ||
157 | ddrc_conf(&ddrc_config); | |
158 | ||
159 | at91_periph_clk_enable(ATMEL_ID_MPDDRC); | |
160 | writel(AT91_PMC_DDR, &pmc->scer); | |
161 | ||
162 | reg = readl(&mpddrc->io_calibr); | |
163 | reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; | |
164 | reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55; | |
165 | reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; | |
166 | reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101); | |
167 | writel(reg, &mpddrc->io_calibr); | |
168 | ||
169 | writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, | |
170 | &mpddrc->rd_data_path); | |
171 | ||
172 | ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); | |
173 | ||
174 | writel(0x3, &mpddrc->cal_mr4); | |
175 | writel(64, &mpddrc->tim_cal); | |
176 | } | |
177 | ||
178 | void at91_pmc_init(void) | |
179 | { | |
180 | u32 tmp; | |
181 | ||
182 | /* | |
183 | * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz | |
184 | * so we need to slow down and configure MCKR accordingly. | |
185 | * This is why we have a special flavor of the switching function. | |
186 | */ | |
187 | tmp = AT91_PMC_MCKR_PLLADIV_2 | | |
188 | AT91_PMC_MCKR_MDIV_3 | | |
189 | AT91_PMC_MCKR_CSS_MAIN; | |
190 | at91_mck_init_down(tmp); | |
191 | ||
192 | tmp = AT91_PMC_PLLAR_29 | | |
193 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | | |
194 | AT91_PMC_PLLXR_MUL(40) | | |
195 | AT91_PMC_PLLXR_DIV(1); | |
196 | at91_plla_init(tmp); | |
197 | ||
198 | tmp = AT91_PMC_MCKR_H32MXDIV | | |
199 | AT91_PMC_MCKR_PLLADIV_2 | | |
200 | AT91_PMC_MCKR_MDIV_3 | | |
201 | AT91_PMC_MCKR_CSS_PLLA; | |
202 | at91_mck_init(tmp); | |
203 | } | |
204 | #endif |