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f196044d BS |
1 | /* |
2 | * Copyright (C) 2014 Atmel | |
3 | * Bo Shen <voice.shen@atmel.com> | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/io.h> | |
10 | #include <asm/arch/at91_common.h> | |
f196044d | 11 | #include <asm/arch/at91_rstc.h> |
0b2a9824 | 12 | #include <asm/arch/atmel_mpddrc.h> |
4f26c8ca | 13 | #include <asm/arch/atmel_usba_udc.h> |
f196044d BS |
14 | #include <asm/arch/gpio.h> |
15 | #include <asm/arch/clk.h> | |
16 | #include <asm/arch/sama5d3_smc.h> | |
17 | #include <asm/arch/sama5d4.h> | |
77d5b407 | 18 | #include <atmel_hlcdc.h> |
f196044d BS |
19 | #include <atmel_mci.h> |
20 | #include <lcd.h> | |
21 | #include <mmc.h> | |
22 | #include <net.h> | |
23 | #include <netdev.h> | |
24 | #include <nand.h> | |
25 | #include <spi.h> | |
02fc64d1 | 26 | #include <version.h> |
f196044d BS |
27 | |
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
30 | #ifdef CONFIG_ATMEL_SPI | |
31 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) | |
32 | { | |
33 | return bus == 0 && cs == 0; | |
34 | } | |
35 | ||
36 | void spi_cs_activate(struct spi_slave *slave) | |
37 | { | |
38 | at91_set_pio_output(AT91_PIO_PORTC, 3, 0); | |
39 | } | |
40 | ||
41 | void spi_cs_deactivate(struct spi_slave *slave) | |
42 | { | |
43 | at91_set_pio_output(AT91_PIO_PORTC, 3, 1); | |
44 | } | |
45 | ||
46 | static void sama5d4_xplained_spi0_hw_init(void) | |
47 | { | |
48 | at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* SPI0_MISO */ | |
49 | at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* SPI0_MOSI */ | |
50 | at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* SPI0_SPCK */ | |
51 | ||
52 | at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */ | |
53 | ||
54 | /* Enable clock */ | |
55 | at91_periph_clk_enable(ATMEL_ID_SPI0); | |
56 | } | |
57 | #endif /* CONFIG_ATMEL_SPI */ | |
58 | ||
59 | #ifdef CONFIG_NAND_ATMEL | |
60 | static void sama5d4_xplained_nand_hw_init(void) | |
61 | { | |
62 | struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; | |
63 | ||
64 | at91_periph_clk_enable(ATMEL_ID_SMC); | |
65 | ||
66 | /* Configure SMC CS3 for NAND */ | |
67 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | | |
68 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), | |
69 | &smc->cs[3].setup); | |
70 | writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | | |
71 | AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), | |
72 | &smc->cs[3].pulse); | |
73 | writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), | |
74 | &smc->cs[3].cycle); | |
75 | writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | | |
76 | AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | | |
77 | AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| | |
78 | AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); | |
79 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | | |
80 | AT91_SMC_MODE_EXNW_DISABLE | | |
81 | AT91_SMC_MODE_DBW_8 | | |
82 | AT91_SMC_MODE_TDF_CYCLE(3), | |
83 | &smc->cs[3].mode); | |
84 | ||
85 | at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ | |
86 | at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ | |
87 | at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ | |
88 | at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ | |
89 | at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ | |
90 | at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ | |
91 | at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ | |
92 | at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ | |
93 | at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ | |
94 | at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ | |
95 | at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ | |
96 | at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ | |
97 | at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ | |
98 | at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ | |
99 | } | |
100 | #endif | |
101 | ||
102 | #ifdef CONFIG_CMD_USB | |
103 | static void sama5d4_xplained_usb_hw_init(void) | |
104 | { | |
105 | at91_set_pio_output(AT91_PIO_PORTE, 11, 1); | |
106 | at91_set_pio_output(AT91_PIO_PORTE, 14, 1); | |
107 | } | |
108 | #endif | |
109 | ||
110 | #ifdef CONFIG_LCD | |
111 | vidinfo_t panel_info = { | |
112 | .vl_col = 480, | |
113 | .vl_row = 272, | |
77d5b407 | 114 | .vl_clk = 9000000, |
f196044d | 115 | .vl_bpix = LCD_BPP, |
f196044d BS |
116 | .vl_tft = 1, |
117 | .vl_hsync_len = 41, | |
118 | .vl_left_margin = 2, | |
119 | .vl_right_margin = 2, | |
120 | .vl_vsync_len = 11, | |
121 | .vl_upper_margin = 2, | |
122 | .vl_lower_margin = 2, | |
123 | .mmio = ATMEL_BASE_LCDC, | |
124 | }; | |
125 | ||
126 | /* No power up/down pin for the LCD pannel */ | |
127 | void lcd_enable(void) { /* Empty! */ } | |
128 | void lcd_disable(void) { /* Empty! */ } | |
129 | ||
130 | unsigned int has_lcdc(void) | |
131 | { | |
132 | return 1; | |
133 | } | |
134 | ||
135 | static void sama5d4_xplained_lcd_hw_init(void) | |
136 | { | |
137 | at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ | |
138 | at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ | |
139 | at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ | |
140 | at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ | |
141 | at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ | |
142 | at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ | |
143 | ||
144 | at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ | |
145 | at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ | |
146 | at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ | |
147 | at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ | |
148 | at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ | |
149 | at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ | |
150 | at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ | |
151 | at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ | |
152 | ||
153 | at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ | |
154 | at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ | |
155 | at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ | |
156 | at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ | |
157 | at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ | |
158 | at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ | |
159 | at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ | |
160 | at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ | |
161 | ||
162 | at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ | |
163 | at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ | |
164 | at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ | |
165 | at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ | |
166 | at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ | |
167 | at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ | |
168 | at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ | |
169 | at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ | |
170 | ||
171 | /* Enable clock */ | |
172 | at91_periph_clk_enable(ATMEL_ID_LCDC); | |
173 | } | |
174 | ||
175 | #ifdef CONFIG_LCD_INFO | |
176 | void lcd_show_board_info(void) | |
177 | { | |
178 | ulong dram_size, nand_size; | |
179 | int i; | |
180 | char temp[32]; | |
181 | ||
02fc64d1 | 182 | lcd_printf("%s\n", U_BOOT_VERSION); |
f196044d BS |
183 | lcd_printf("2014 ATMEL Corp\n"); |
184 | lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), | |
185 | strmhz(temp, get_cpu_clk_rate())); | |
186 | ||
187 | dram_size = 0; | |
188 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) | |
189 | dram_size += gd->bd->bi_dram[i].size; | |
190 | ||
191 | nand_size = 0; | |
192 | #ifdef CONFIG_NAND_ATMEL | |
193 | for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) | |
194 | nand_size += nand_info[i].size; | |
195 | #endif | |
196 | lcd_printf("%ld MB SDRAM, %ld MB NAND\n", | |
197 | dram_size >> 20, nand_size >> 20); | |
198 | } | |
199 | #endif /* CONFIG_LCD_INFO */ | |
200 | ||
201 | #endif /* CONFIG_LCD */ | |
202 | ||
203 | #ifdef CONFIG_GENERIC_ATMEL_MCI | |
204 | void sama5d4_xplained_mci1_hw_init(void) | |
205 | { | |
206 | at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ | |
207 | at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ | |
208 | at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ | |
209 | at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ | |
210 | at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ | |
211 | at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ | |
212 | ||
213 | /* | |
214 | * As the mci io internal pull down is too strong, so if the io needs | |
215 | * external pull up, the pull up resistor will be very small, if so | |
216 | * the power consumption will increase, so disable the interanl pull | |
217 | * down to save the power. | |
218 | */ | |
219 | at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); | |
220 | at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); | |
221 | at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); | |
222 | at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); | |
223 | at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); | |
224 | at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); | |
225 | ||
226 | /* Enable clock */ | |
227 | at91_periph_clk_enable(ATMEL_ID_MCI1); | |
228 | } | |
229 | ||
230 | int board_mmc_init(bd_t *bis) | |
231 | { | |
66bfce55 BS |
232 | /* Enable the power supply */ |
233 | at91_set_pio_output(AT91_PIO_PORTE, 4, 0); | |
234 | ||
f196044d BS |
235 | return atmel_mci_init((void *)ATMEL_BASE_MCI1); |
236 | } | |
237 | #endif /* CONFIG_GENERIC_ATMEL_MCI */ | |
238 | ||
239 | #ifdef CONFIG_MACB | |
240 | void sama5d4_xplained_macb0_hw_init(void) | |
241 | { | |
242 | at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ | |
243 | at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ | |
244 | at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ | |
245 | at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ | |
246 | at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ | |
247 | at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ | |
248 | at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ | |
249 | at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ | |
250 | at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ | |
251 | at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ | |
252 | ||
253 | /* Enable clock */ | |
254 | at91_periph_clk_enable(ATMEL_ID_GMAC0); | |
255 | } | |
256 | #endif | |
257 | ||
258 | static void sama5d4_xplained_serial3_hw_init(void) | |
259 | { | |
260 | at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ | |
261 | at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ | |
262 | ||
263 | /* Enable clock */ | |
264 | at91_periph_clk_enable(ATMEL_ID_USART3); | |
265 | } | |
266 | ||
267 | int board_early_init_f(void) | |
268 | { | |
269 | at91_periph_clk_enable(ATMEL_ID_PIOA); | |
270 | at91_periph_clk_enable(ATMEL_ID_PIOB); | |
271 | at91_periph_clk_enable(ATMEL_ID_PIOC); | |
272 | at91_periph_clk_enable(ATMEL_ID_PIOD); | |
273 | at91_periph_clk_enable(ATMEL_ID_PIOE); | |
274 | ||
275 | sama5d4_xplained_serial3_hw_init(); | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | int board_init(void) | |
281 | { | |
282 | /* adress of boot parameters */ | |
283 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | |
284 | ||
285 | #ifdef CONFIG_ATMEL_SPI | |
286 | sama5d4_xplained_spi0_hw_init(); | |
287 | #endif | |
288 | #ifdef CONFIG_NAND_ATMEL | |
289 | sama5d4_xplained_nand_hw_init(); | |
290 | #endif | |
291 | #ifdef CONFIG_GENERIC_ATMEL_MCI | |
292 | sama5d4_xplained_mci1_hw_init(); | |
293 | #endif | |
294 | #ifdef CONFIG_MACB | |
295 | sama5d4_xplained_macb0_hw_init(); | |
296 | #endif | |
297 | #ifdef CONFIG_LCD | |
298 | sama5d4_xplained_lcd_hw_init(); | |
299 | #endif | |
300 | #ifdef CONFIG_CMD_USB | |
301 | sama5d4_xplained_usb_hw_init(); | |
302 | #endif | |
4f26c8ca BS |
303 | #ifdef CONFIG_USB_GADGET_ATMEL_USBA |
304 | at91_udp_hw_init(); | |
305 | #endif | |
f196044d BS |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | int dram_init(void) | |
311 | { | |
312 | gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, | |
313 | CONFIG_SYS_SDRAM_SIZE); | |
314 | return 0; | |
315 | } | |
316 | ||
317 | int board_eth_init(bd_t *bis) | |
318 | { | |
319 | int rc = 0; | |
320 | ||
321 | #ifdef CONFIG_MACB | |
322 | rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); | |
323 | #endif | |
324 | ||
4f26c8ca BS |
325 | #ifdef CONFIG_USB_GADGET_ATMEL_USBA |
326 | usba_udc_probe(&pdata); | |
327 | #ifdef CONFIG_USB_ETH_RNDIS | |
328 | usb_eth_initialize(bis); | |
329 | #endif | |
330 | #endif | |
331 | ||
f196044d BS |
332 | return rc; |
333 | } | |
0b2a9824 BS |
334 | |
335 | /* SPL */ | |
336 | #ifdef CONFIG_SPL_BUILD | |
337 | void spl_board_init(void) | |
338 | { | |
339 | #ifdef CONFIG_SYS_USE_MMC | |
340 | sama5d4_xplained_mci1_hw_init(); | |
341 | #elif CONFIG_SYS_USE_NANDFLASH | |
342 | sama5d4_xplained_nand_hw_init(); | |
343 | #elif CONFIG_SYS_USE_SERIALFLASH | |
344 | sama5d4_xplained_spi0_hw_init(); | |
345 | #endif | |
346 | } | |
347 | ||
7e8702a0 | 348 | static void ddr2_conf(struct atmel_mpddrc_config *ddr2) |
0b2a9824 BS |
349 | { |
350 | ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); | |
351 | ||
352 | ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | | |
353 | ATMEL_MPDDRC_CR_NR_ROW_14 | | |
354 | ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | | |
355 | ATMEL_MPDDRC_CR_NB_8BANKS | | |
356 | ATMEL_MPDDRC_CR_NDQS_DISABLED | | |
357 | ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | | |
358 | ATMEL_MPDDRC_CR_UNAL_SUPPORTED); | |
359 | ||
360 | ddr2->rtr = 0x2b0; | |
361 | ||
362 | ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | | |
363 | 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | | |
364 | 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | | |
365 | 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | | |
366 | 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | | |
367 | 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | | |
368 | 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | | |
369 | 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); | |
370 | ||
371 | ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | | |
372 | 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | | |
373 | 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | | |
374 | 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); | |
375 | ||
376 | ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | | |
377 | 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | | |
378 | 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | | |
379 | 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | | |
380 | 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); | |
381 | } | |
382 | ||
383 | void mem_init(void) | |
384 | { | |
7e8702a0 | 385 | struct atmel_mpddrc_config ddr2; |
0b2a9824 BS |
386 | |
387 | ddr2_conf(&ddr2); | |
388 | ||
70341e2e | 389 | /* Enable MPDDR clock */ |
0b2a9824 | 390 | at91_periph_clk_enable(ATMEL_ID_MPDDRC); |
70341e2e | 391 | at91_system_clk_enable(AT91_PMC_DDR); |
0b2a9824 BS |
392 | |
393 | /* DDRAM2 Controller initialize */ | |
0c01c3e8 | 394 | ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); |
0b2a9824 BS |
395 | } |
396 | ||
397 | void at91_pmc_init(void) | |
398 | { | |
0b2a9824 BS |
399 | u32 tmp; |
400 | ||
401 | tmp = AT91_PMC_PLLAR_29 | | |
402 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | | |
403 | AT91_PMC_PLLXR_MUL(87) | | |
404 | AT91_PMC_PLLXR_DIV(1); | |
405 | at91_plla_init(tmp); | |
406 | ||
ede86ed2 | 407 | at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); |
0b2a9824 BS |
408 | |
409 | tmp = AT91_PMC_MCKR_H32MXDIV | | |
410 | AT91_PMC_MCKR_PLLADIV_2 | | |
411 | AT91_PMC_MCKR_MDIV_3 | | |
412 | AT91_PMC_MCKR_CSS_PLLA; | |
413 | at91_mck_init(tmp); | |
414 | } | |
415 | #endif |