[people/ms/u-boot.git] / board / atum8548 / atum8548.c

/*
 * Copyright 2007
 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
 *
 * Copyright 2007 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/immap_fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif

long int fixed_sdram(void);

int board_early_init_f (void)
{
	return 0;
}

int checkboard (void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);

	if ((uint)&gur->porpllsr != 0xe00e0000) {
		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
	}
	printf ("Board: ATUM8548\n");

	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
	ecm->eeer = 0xffffffff;		/* Enable ecm errors */

	return 0;
}

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 ************************************************************************/
long int fixed_sdram (void)
{
	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);

	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
    #if defined (CONFIG_DDR_ECC)
	ddr->err_disable = 0x0000000D;
	ddr->err_sbe = 0x00ff0000;
    #endif
	asm("sync;isync;msync");
	udelay(500);
    #if defined (CONFIG_DDR_ECC)
	/* Enable ECC checking */
	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
    #else
	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
    #endif
	asm("sync; isync; msync");
	udelay(500);
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
}
#endif	/* !defined(CONFIG_SPD_EEPROM) */

phys_size_t
initdram(int board_type)
{
	long dram_size = 0;

	puts("Initializing\n");

#if defined(CONFIG_SPD_EEPROM)
	puts("fsl_ddr_sdram\n");
	dram_size = fsl_ddr_sdram();
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;
#else
	puts("fixed_sdram\n");
	dram_size = fixed_sdram ();
#endif

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif
	puts("    DDR: ");
	return dram_size;
}

#if defined(CONFIG_SYS_DRAM_TEST)
int
testdram(void)
{
	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
	uint *p;

	printf("Testing DRAM from 0x%08x to 0x%08x\n",
	       CONFIG_SYS_MEMTEST_START,
	       CONFIG_SYS_MEMTEST_END);

	printf("DRAM test phase 1:\n");
	for (p = pstart; p < pend; p++) {
		printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
		*p = 0xaaaaaaaa;
	}

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test phase 2:\n");
	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("DRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	printf("DRAM test passed.\n");
	return 0;
}
#endif

#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif

#ifdef CONFIG_PCI2
static struct pci_controller pci2_hose;
#endif

#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif

int first_free_busno=0;

void
pci_init_board(void)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

	uint devdisr = gur->devdisr;
	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;

	debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
		devdisr, io_sel, host_agent);

	/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
	gur->clkocr  |= MPC85xx_ATUM_CLKOCR;

	if (io_sel & 1) {
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
			printf ("    eTSEC1 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
			printf ("    eTSEC2 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
			printf ("    eTSEC3 is in sgmii mode.\n");
		if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
			printf ("    eTSEC4 is in sgmii mode.\n");
	}

#ifdef CONFIG_PCIE1
 {
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pcie1_hose;
	int pcie_ep = (host_agent == 5);
	int pcie_configured  = io_sel & 6;

	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
		printf ("\n    PCIE1 connected to slot as %s (base address %x)",
			pcie_ep ? "End Point" : "Root Complex",
			(uint)pci);
		if (pci->pme_msg_det) {
			pci->pme_msg_det = 0xffffffff;
			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
		}
		printf ("\n");

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CONFIG_SYS_PCI_MEMORY_BUS,
			       CONFIG_SYS_PCI_MEMORY_PHYS,
			       CONFIG_SYS_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CONFIG_SYS_PCIE1_MEM_BASE,
			       CONFIG_SYS_PCIE1_MEM_PHYS,
			       CONFIG_SYS_PCIE1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CONFIG_SYS_PCIE1_IO_BASE,
			       CONFIG_SYS_PCIE1_IO_PHYS,
			       CONFIG_SYS_PCIE1_IO_SIZE,
			       PCI_REGION_IO);

		hose->region_count = 3;
#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
		/* outbound memory */
		pci_set_region(hose->regions + 3,
			       CONFIG_SYS_PCIE1_MEM_BASE2,
			       CONFIG_SYS_PCIE1_MEM_PHYS2,
			       CONFIG_SYS_PCIE1_MEM_SIZE2,
			       PCI_REGION_MEM);
		hose->region_count++;
#endif
		hose->first_busno=first_free_busno;

		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);

		first_free_busno=hose->last_busno+1;
		printf("    PCIE1 on bus %02x - %02x\n",
		       hose->first_busno,hose->last_busno);

	} else {
		printf ("    PCIE1: disabled\n");
	}

 }
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif

#ifdef CONFIG_PCI1
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci1_hose;

	uint pci_agent = (host_agent == 6);
	uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */

	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
		printf ("\n    PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
			(pci_32) ? 32 : 64,
			(pci_speed == 33333000) ? "33" :
			(pci_speed == 66666000) ? "66" : "unknown",
			pci_clk_sel ? "sync" : "async",
			pci_agent ? "agent" : "host",
			pci_arb ? "arbiter" : "external-arbiter",
			(uint)pci
			);

		/* inbound */
		pci_set_region(hose->regions + 0,
			       CONFIG_SYS_PCI_MEMORY_BUS,
			       CONFIG_SYS_PCI_MEMORY_PHYS,
			       CONFIG_SYS_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		/* outbound memory */
		pci_set_region(hose->regions + 1,
			       CONFIG_SYS_PCI1_MEM_BASE,
			       CONFIG_SYS_PCI1_MEM_PHYS,
			       CONFIG_SYS_PCI1_MEM_SIZE,
			       PCI_REGION_MEM);

		/* outbound io */
		pci_set_region(hose->regions + 2,
			       CONFIG_SYS_PCI1_IO_BASE,
			       CONFIG_SYS_PCI1_IO_PHYS,
			       CONFIG_SYS_PCI1_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = 3;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI1 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI1: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif

#ifdef CONFIG_PCI2
{
	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
	extern void fsl_pci_init(struct pci_controller *hose);
	struct pci_controller *hose = &pci2_hose;

	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
		pci_set_region(hose->regions + 0,
			       CONFIG_SYS_PCI_MEMORY_BUS,
			       CONFIG_SYS_PCI_MEMORY_PHYS,
			       CONFIG_SYS_PCI_MEMORY_SIZE,
			       PCI_REGION_MEM | PCI_REGION_MEMORY);

		pci_set_region(hose->regions + 1,
			       CONFIG_SYS_PCI2_MEM_BASE,
			       CONFIG_SYS_PCI2_MEM_PHYS,
			       CONFIG_SYS_PCI2_MEM_SIZE,
			       PCI_REGION_MEM);

		pci_set_region(hose->regions + 2,
			       CONFIG_SYS_PCI2_IO_BASE,
			       CONFIG_SYS_PCI2_IO_PHYS,
			       CONFIG_SYS_PCI2_IO_SIZE,
			       PCI_REGION_IO);
		hose->region_count = 3;
		hose->first_busno=first_free_busno;
		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);

		fsl_pci_init(hose);
		first_free_busno=hose->last_busno+1;
		printf ("PCI2 on bus %02x - %02x\n",
			hose->first_busno,hose->last_busno);
	} else {
		printf ("    PCI2: disabled\n");
	}
}
#else
	gur->devdisr |= MPC85xx_DEVDISR_PCI2;
#endif
}


int last_stage_init(void)
{
	int ic = icache_status ();
	printf ("icache_status: %d\n", ic);
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP)

void
ft_board_setup(void *blob, bd_t *bd)
{
	int node, tmp[2];
	const char *path;

	ft_cpu_setup(blob, bd);

	node = fdt_path_offset(blob, "/aliases");
	tmp[0] = 0;
	if (node >= 0) {
#ifdef CONFIG_PCI1
		path = fdt_getprop(blob, node, "pci0", NULL);
		if (path) {
			tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_PCI2
		path = fdt_getprop(blob, node, "pci1", NULL);
		if (path) {
			tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
#ifdef CONFIG_PCIE1
		path = fdt_getprop(blob, node, "pci2", NULL);
		if (path) {
			tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
			do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
		}
#endif
	}
}
#endif
Commit	Line	Data
b964e936	1	/*
	2	* Copyright 2007
	3	* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
	4	*
	5	* Copyright 2007 Freescale Semiconductor, Inc.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#include <common.h>
	27	#include <command.h>
	28	#include <pci.h>
	29	#include <asm/processor.h>
	30	#include <asm/immap_85xx.h>
	31	#include <asm/immap_fsl_pci.h>
a947e4c7	32	#include <asm/fsl_ddr_sdram.h>
b964e936	33	#include <asm/io.h>
a947e4c7	34	#include <asm/mmu.h>
a30a549a	35	#include <spd_sdram.h>
b964e936	36	#include <miiphy.h>
	37	#include <libfdt.h>
	38	#include <fdt_support.h>
	39
	40	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	41	extern void ddr_enable_ecc(unsigned int dram_size);
	42	#endif
	43
b964e936	44	long int fixed_sdram(void);
	45
	46	int board_early_init_f (void)
	47	{
	48	return 0;
	49	}
	50
	51	int checkboard (void)
	52	{
6d0f6bcf JCPV	53	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	54	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	55	volatile ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
b964e936	56
b964e936	57	if ((uint)&gur->porpllsr != 0xe00e0000) {
9b55a253	58	printf("immap size error %lx\n",(ulong)&gur->porpllsr);
b964e936	59	}
	60	printf ("Board: ATUM8548\n");
	61
	62	lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
	63	lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
	64	ecm->eedr = 0xffffffff; /* Clear ecm errors */
	65	ecm->eeer = 0xffffffff; /* Enable ecm errors */
	66
	67	return 0;
	68	}
	69
	70	#if !defined(CONFIG_SPD_EEPROM)
	71	/*************************************************************************
	72	* fixed sdram init -- doesn't use serial presence detect.
	73	************************************************************************/
	74	long int fixed_sdram (void)
	75	{
6d0f6bcf JCPV	76	volatile ccsr_ddr_t ddr= (void )(CONFIG_SYS_MPC85xx_DDR_ADDR);
	77
	78	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
	79	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
	80	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
	81	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
	82	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
	83	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
	84	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
b964e936	85	#if defined (CONFIG_DDR_ECC)
	86	ddr->err_disable = 0x0000000D;
	87	ddr->err_sbe = 0x00ff0000;
	88	#endif
	89	asm("sync;isync;msync");
	90	udelay(500);
	91	#if defined (CONFIG_DDR_ECC)
	92	/* Enable ECC checking */
6d0f6bcf	93	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL \| 0x20000000);
b964e936	94	#else
6d0f6bcf	95	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
b964e936	96	#endif
	97	asm("sync; isync; msync");
	98	udelay(500);
6d0f6bcf	99	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
b964e936	100	}
	101	#endif /* !defined(CONFIG_SPD_EEPROM) */
	102
9973e3c6	103	phys_size_t
b964e936	104	initdram(int board_type)
	105	{
	106	long dram_size = 0;
	107
	108	puts("Initializing\n");
	109
	110	#if defined(CONFIG_SPD_EEPROM)
a947e4c7 KG	111	puts("fsl_ddr_sdram\n");
	112	dram_size = fsl_ddr_sdram();
	113	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	114	dram_size *= 0x100000;
b964e936	115	#else
	116	puts("fixed_sdram\n");
	117	dram_size = fixed_sdram ();
	118	#endif
	119
	120	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	121	/*
	122	* Initialize and enable DDR ECC.
	123	*/
	124	ddr_enable_ecc(dram_size);
	125	#endif
	126	puts(" DDR: ");
	127	return dram_size;
	128	}
	129
6d0f6bcf	130	#if defined(CONFIG_SYS_DRAM_TEST)
b964e936	131	int
	132	testdram(void)
	133	{
6d0f6bcf JCPV	134	uint pstart = (uint ) CONFIG_SYS_MEMTEST_START;
6d0f6bcf JCPV	135	uint pend = (uint ) CONFIG_SYS_MEMTEST_END;
b964e936	136	uint *p;
	137
	138	printf("Testing DRAM from 0x%08x to 0x%08x\n",
6d0f6bcf JCPV	139	CONFIG_SYS_MEMTEST_START,
6d0f6bcf JCPV	140	CONFIG_SYS_MEMTEST_END);
b964e936	141
	142	printf("DRAM test phase 1:\n");
	143	for (p = pstart; p < pend; p++) {
	144	printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
	145	*p = 0xaaaaaaaa;
d3a6532c	146	}
b964e936	147
	148	for (p = pstart; p < pend; p++) {
	149	if (*p != 0xaaaaaaaa) {
	150	printf ("DRAM test fails at: %08x\n", (uint) p);
	151	return 1;
	152	}
	153	}
	154
	155	printf("DRAM test phase 2:\n");
	156	for (p = pstart; p < pend; p++)
	157	*p = 0x55555555;
	158
	159	for (p = pstart; p < pend; p++) {
	160	if (*p != 0x55555555) {
	161	printf ("DRAM test fails at: %08x\n", (uint) p);
	162	return 1;
	163	}
	164	}
	165
	166	printf("DRAM test passed.\n");
	167	return 0;
	168	}
	169	#endif
	170
	171	#ifdef CONFIG_PCI1
	172	static struct pci_controller pci1_hose;
	173	#endif
	174
	175	#ifdef CONFIG_PCI2
	176	static struct pci_controller pci2_hose;
	177	#endif
	178
	179	#ifdef CONFIG_PCIE1
	180	static struct pci_controller pcie1_hose;
	181	#endif
	182
	183	int first_free_busno=0;
	184
	185	void
	186	pci_init_board(void)
	187	{
6d0f6bcf	188	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
b964e936	189
	190	uint devdisr = gur->devdisr;
	191	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
	192	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
	193
	194	debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
	195	devdisr, io_sel, host_agent);
	196
d3a6532c	197	/* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
b964e936	198	gur->clkocr \|= MPC85xx_ATUM_CLKOCR;
	199
	200	if (io_sel & 1) {
	201	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
	202	printf (" eTSEC1 is in sgmii mode.\n");
	203	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
	204	printf (" eTSEC2 is in sgmii mode.\n");
	205	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
	206	printf (" eTSEC3 is in sgmii mode.\n");
	207	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
	208	printf (" eTSEC4 is in sgmii mode.\n");
	209	}
	210
	211	#ifdef CONFIG_PCIE1
	212	{
6d0f6bcf	213	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCIE1_ADDR;
b964e936	214	extern void fsl_pci_init(struct pci_controller *hose);
	215	struct pci_controller *hose = &pcie1_hose;
	216	int pcie_ep = (host_agent == 5);
	217	int pcie_configured = io_sel & 6;
	218
	219	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
	220	printf ("\n PCIE1 connected to slot as %s (base address %x)",
	221	pcie_ep ? "End Point" : "Root Complex",
	222	(uint)pci);
	223	if (pci->pme_msg_det) {
	224	pci->pme_msg_det = 0xffffffff;
	225	debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
	226	}
	227	printf ("\n");
	228
	229	/* inbound */
	230	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	231	CONFIG_SYS_PCI_MEMORY_BUS,
	232	CONFIG_SYS_PCI_MEMORY_PHYS,
	233	CONFIG_SYS_PCI_MEMORY_SIZE,
b964e936	234	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	235
	236	/* outbound memory */
	237	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	238	CONFIG_SYS_PCIE1_MEM_BASE,
	239	CONFIG_SYS_PCIE1_MEM_PHYS,
	240	CONFIG_SYS_PCIE1_MEM_SIZE,
b964e936	241	PCI_REGION_MEM);
	242
	243	/* outbound io */
	244	pci_set_region(hose->regions + 2,
6d0f6bcf JCPV	245	CONFIG_SYS_PCIE1_IO_BASE,
	246	CONFIG_SYS_PCIE1_IO_PHYS,
	247	CONFIG_SYS_PCIE1_IO_SIZE,
b964e936	248	PCI_REGION_IO);
	249
	250	hose->region_count = 3;
6d0f6bcf	251	#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
b964e936	252	/* outbound memory */
b964e936	253	pci_set_region(hose->regions + 3,
6d0f6bcf JCPV	254	CONFIG_SYS_PCIE1_MEM_BASE2,
	255	CONFIG_SYS_PCIE1_MEM_PHYS2,
	256	CONFIG_SYS_PCIE1_MEM_SIZE2,
b964e936	257	PCI_REGION_MEM);
	258	hose->region_count++;
	259	#endif
	260	hose->first_busno=first_free_busno;
	261
	262	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	263
	264	fsl_pci_init(hose);
	265
	266	first_free_busno=hose->last_busno+1;
	267	printf(" PCIE1 on bus %02x - %02x\n",
	268	hose->first_busno,hose->last_busno);
	269
	270	} else {
	271	printf (" PCIE1: disabled\n");
	272	}
	273
	274	}
	275	#else
	276	gur->devdisr \|= MPC85xx_DEVDISR_PCIE; /* disable */
	277	#endif
	278
	279	#ifdef CONFIG_PCI1
	280	{
6d0f6bcf	281	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI1_ADDR;
b964e936	282	extern void fsl_pci_init(struct pci_controller *hose);
	283	struct pci_controller *hose = &pci1_hose;
	284
	285	uint pci_agent = (host_agent == 6);
	286	uint pci_speed = 33333000; /get_clock_freq (); PCI PSPEED in [4:5] /
	287	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
	288	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
	289	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
	290
	291	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
	292	printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
	293	(pci_32) ? 32 : 64,
	294	(pci_speed == 33333000) ? "33" :
	295	(pci_speed == 66666000) ? "66" : "unknown",
	296	pci_clk_sel ? "sync" : "async",
	297	pci_agent ? "agent" : "host",
	298	pci_arb ? "arbiter" : "external-arbiter",
	299	(uint)pci
	300	);
	301
	302	/* inbound */
	303	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	304	CONFIG_SYS_PCI_MEMORY_BUS,
	305	CONFIG_SYS_PCI_MEMORY_PHYS,
	306	CONFIG_SYS_PCI_MEMORY_SIZE,
b964e936	307	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	308
	309	/* outbound memory */
	310	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	311	CONFIG_SYS_PCI1_MEM_BASE,
	312	CONFIG_SYS_PCI1_MEM_PHYS,
	313	CONFIG_SYS_PCI1_MEM_SIZE,
b964e936	314	PCI_REGION_MEM);
	315
	316	/* outbound io */
	317	pci_set_region(hose->regions + 2,
6d0f6bcf JCPV	318	CONFIG_SYS_PCI1_IO_BASE,
	319	CONFIG_SYS_PCI1_IO_PHYS,
	320	CONFIG_SYS_PCI1_IO_SIZE,
b964e936	321	PCI_REGION_IO);
	322	hose->region_count = 3;
	323	hose->first_busno=first_free_busno;
	324	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	325
	326	fsl_pci_init(hose);
	327	first_free_busno=hose->last_busno+1;
	328	printf ("PCI1 on bus %02x - %02x\n",
	329	hose->first_busno,hose->last_busno);
	330	} else {
	331	printf (" PCI1: disabled\n");
	332	}
	333	}
	334	#else
	335	gur->devdisr \|= MPC85xx_DEVDISR_PCI1; /* disable */
	336	#endif
	337
	338	#ifdef CONFIG_PCI2
	339	{
6d0f6bcf	340	volatile ccsr_fsl_pci_t pci = (ccsr_fsl_pci_t ) CONFIG_SYS_PCI2_ADDR;
b964e936	341	extern void fsl_pci_init(struct pci_controller *hose);
	342	struct pci_controller *hose = &pci2_hose;
	343
	344	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
	345	pci_set_region(hose->regions + 0,
6d0f6bcf JCPV	346	CONFIG_SYS_PCI_MEMORY_BUS,
	347	CONFIG_SYS_PCI_MEMORY_PHYS,
	348	CONFIG_SYS_PCI_MEMORY_SIZE,
b964e936	349	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	350
	351	pci_set_region(hose->regions + 1,
6d0f6bcf JCPV	352	CONFIG_SYS_PCI2_MEM_BASE,
	353	CONFIG_SYS_PCI2_MEM_PHYS,
	354	CONFIG_SYS_PCI2_MEM_SIZE,
b964e936	355	PCI_REGION_MEM);
	356
	357	pci_set_region(hose->regions + 2,
6d0f6bcf JCPV	358	CONFIG_SYS_PCI2_IO_BASE,
	359	CONFIG_SYS_PCI2_IO_PHYS,
	360	CONFIG_SYS_PCI2_IO_SIZE,
b964e936	361	PCI_REGION_IO);
	362	hose->region_count = 3;
	363	hose->first_busno=first_free_busno;
	364	pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
	365
	366	fsl_pci_init(hose);
	367	first_free_busno=hose->last_busno+1;
	368	printf ("PCI2 on bus %02x - %02x\n",
	369	hose->first_busno,hose->last_busno);
	370	} else {
	371	printf (" PCI2: disabled\n");
	372	}
	373	}
	374	#else
	375	gur->devdisr \|= MPC85xx_DEVDISR_PCI2;
	376	#endif
	377	}
	378
	379
	380	int last_stage_init(void)
	381	{
d3a6532c	382	int ic = icache_status ();
b964e936	383	printf ("icache_status: %d\n", ic);
	384	return 0;
	385	}
	386
	387	#if defined(CONFIG_OF_BOARD_SETUP)
	388
	389	void
	390	ft_board_setup(void blob, bd_t bd)
	391	{
	392	int node, tmp[2];
	393	const char *path;
	394
	395	ft_cpu_setup(blob, bd);
	396
	397	node = fdt_path_offset(blob, "/aliases");
	398	tmp[0] = 0;
	399	if (node >= 0) {
	400	#ifdef CONFIG_PCI1
	401	path = fdt_getprop(blob, node, "pci0", NULL);
	402	if (path) {
	403	tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
	404	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	405	}
	406	#endif
	407	#ifdef CONFIG_PCI2
	408	path = fdt_getprop(blob, node, "pci1", NULL);
	409	if (path) {
	410	tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
	411	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	412	}
	413	#endif
	414	#ifdef CONFIG_PCIE1
	415	path = fdt_getprop(blob, node, "pci2", NULL);
	416	if (path) {
	417	tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
	418	do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
	419	}
	420	#endif
	421	}
	422	}
	423	#endif