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Commit | Line | Data |
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b1c0c736 TR |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
ed900c55 | 4 | * (C) Copyright 2011-2012 |
b1c0c736 TR |
5 | * Avionic Design GmbH <www.avionic-design.de> |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
b1c0c736 TR |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <ns16550.h> | |
12 | #include <asm/io.h> | |
13 | #include <asm/gpio.h> | |
b1c0c736 | 14 | #include <asm/arch/clock.h> |
f4483021 | 15 | #include <asm/arch/funcmux.h> |
b1c0c736 | 16 | #include <asm/arch/pinmux.h> |
150c2493 TW |
17 | #include <asm/arch/tegra.h> |
18 | #include <asm/arch-tegra/board.h> | |
19 | #include <asm/arch-tegra/clk_rst.h> | |
150c2493 TW |
20 | #include <asm/arch-tegra/sys_proto.h> |
21 | #include <asm/arch-tegra/uart.h> | |
b1c0c736 | 22 | |
22d58506 TR |
23 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
24 | void gpio_early_init(void) | |
25 | { | |
26 | gpio_request(GPIO_PI4, NULL); | |
27 | gpio_direction_output(GPIO_PI4, 1); | |
28 | } | |
29 | #endif | |
30 | ||
1e2d7859 | 31 | #ifdef CONFIG_TEGRA_MMC |
b1c0c736 TR |
32 | /* |
33 | * Routine: pin_mux_mmc | |
34 | * Description: setup the pin muxes/tristate values for the SDMMC(s) | |
35 | */ | |
c9aa831e | 36 | void pin_mux_mmc(void) |
b1c0c736 | 37 | { |
f4483021 | 38 | funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); |
79254543 TR |
39 | /* for write-protect GPIO PI6 */ |
40 | pinmux_tristate_disable(PINGRP_ATA); | |
ed900c55 TR |
41 | /* for CD GPIO PH2 */ |
42 | pinmux_tristate_disable(PINGRP_ATD); | |
b1c0c736 | 43 | } |
b1c0c736 | 44 | #endif |