[people/ms/u-boot.git] / board / avnet / v5fx30teval / xparameters.h

/*
 * (C) Copyright 2008
 * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
 * This work has been supported by: QTechnology  http://qtec.com/
 * based on xparameters.h by Xilinx
 *
 * SPDX-License-Identifier:	GPL-2.0+
*/

#ifndef XPARAMETER_H
#define XPARAMETER_H

#define XPAR_DDR2_SDRAM_MEM_BASEADDR	0x00000000
#define XPAR_INTC_0_BASEADDR		0x81800000
#define XPAR_UARTLITE_0_BASEADDR	0x84000000
#define XPAR_FLASH_MEM0_BASEADDR	0xFF000000
#define XPAR_PLB_CLOCK_FREQ_HZ		100000000
#define XPAR_CORE_CLOCK_FREQ_HZ		400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS	13
#define XPAR_UARTLITE_0_BAUDRATE	9600

#endif
Commit	Line	Data
e07f4a80 RR	1	/*
	2	* (C) Copyright 2008
	3	* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es
	4	* This work has been supported by: QTechnology http://qtec.com/
	5	* based on xparameters.h by Xilinx
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
e07f4a80 RR	8	*/
	9
	10	#ifndef XPARAMETER_H
	11	#define XPARAMETER_H
	12
	13	#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
	14	#define XPAR_INTC_0_BASEADDR 0x81800000
	15	#define XPAR_UARTLITE_0_BASEADDR 0x84000000
	16	#define XPAR_FLASH_MEM0_BASEADDR 0xFF000000
	17	#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
	18	#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
	19	#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
	20	#define XPAR_UARTLITE_0_BAUDRATE 9600
	21
	22	#endif