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Add support for BC3450 board
[people/ms/u-boot.git] / board / bc3450 / bc3450.c
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6ca24c64 1/*
2 * -- Version 1.1 --
3 *
4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004
8 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 *
10 * (C) Copyright 2004-2005
11 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
12 *
13 * (C) Copyright 2006
14 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
15 *
16 * History:
17 * 1.1 - improved SM501 init to meet spec timing
18 *
19 * See file CREDITS for list of people who contributed to this
20 * project.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
26 *
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
31 *
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 * MA 02111-1307 USA
36 */
37
38#include <common.h>
39#include <mpc5xxx.h>
40#include <pci.h>
41
42#ifdef CONFIG_VIDEO_SM501
43#include <sm501.h>
44#endif
45
46#if defined(CONFIG_MPC5200_DDR)
47#include "mt46v16m16-75.h"
48#else
49#include "mt48lc16m16a2-75.h"
50#endif
51
52#ifdef CONFIG_RTC_MPC5200
53#include <rtc.h>
54#endif
55
56#ifdef CONFIG_PS2MULT
57void ps2mult_early_init(void);
58#endif
59
60#ifndef CFG_RAMBOOT
61static void sdram_start (int hi_addr)
62{
63 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
64
65 /* unlock mode register */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
67 hi_addr_bit;
68 __asm__ volatile ("sync");
69
70 /* precharge all banks */
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
72 hi_addr_bit;
73 __asm__ volatile ("sync");
74
75#if SDRAM_DDR
76 /* set mode register: extended mode */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
78 __asm__ volatile ("sync");
79
80 /* set mode register: reset DLL */
81 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
82 __asm__ volatile ("sync");
83#endif
84
85 /* precharge all banks */
86 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
87 hi_addr_bit;
88 __asm__ volatile ("sync");
89
90 /* auto refresh */
91 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
92 hi_addr_bit;
93 __asm__ volatile ("sync");
94
95 /* set mode register */
96 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
97 __asm__ volatile ("sync");
98
99 /* normal operation */
100 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
101 __asm__ volatile ("sync");
102}
103#endif
104
105/*
106 * ATTENTION: Although partially referenced initdram does NOT make real use
107 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
108 * is something else than 0x00000000.
109 */
110
111#if defined(CONFIG_MPC5200)
112long int initdram (int board_type)
113{
114 ulong dramsize = 0;
115 ulong dramsize2 = 0;
116#ifndef CFG_RAMBOOT
117 ulong test1, test2;
118
119 /* setup SDRAM chip selects */
120 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
121 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
122 __asm__ volatile ("sync");
123
124 /* setup config registers */
125 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
126 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
127 __asm__ volatile ("sync");
128
129#if SDRAM_DDR
130 /* set tap delay */
131 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
132 __asm__ volatile ("sync");
133#endif
134
135 /* find RAM size using SDRAM CS0 only */
136 sdram_start(0);
137 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
138 sdram_start(1);
139 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
140 if (test1 > test2) {
141 sdram_start(0);
142 dramsize = test1;
143 } else {
144 dramsize = test2;
145 }
146
147 /* memory smaller than 1MB is impossible */
148 if (dramsize < (1 << 20)) {
149 dramsize = 0;
150 }
151
152 /* set SDRAM CS0 size according to the amount of RAM found */
153 if (dramsize > 0) {
154 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
155 __builtin_ffs(dramsize >> 20) - 1;
156 } else {
157 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
158 }
159
160 /* let SDRAM CS1 start right after CS0 */
161 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
162
163 /* find RAM size using SDRAM CS1 only */
164 sdram_start(0);
165 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
166 sdram_start(1);
167 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
168 if (test1 > test2) {
169 sdram_start(0);
170 dramsize2 = test1;
171 } else {
172 dramsize2 = test2;
173 }
174
175 /* memory smaller than 1MB is impossible */
176 if (dramsize2 < (1 << 20)) {
177 dramsize2 = 0;
178 }
179
180 /* set SDRAM CS1 size according to the amount of RAM found */
181 if (dramsize2 > 0) {
182 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
183 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
184 } else {
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
186 }
187
188#else /* CFG_RAMBOOT */
189
190 /* retrieve size of memory connected to SDRAM CS0 */
191 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
192 if (dramsize >= 0x13) {
193 dramsize = (1 << (dramsize - 0x13)) << 20;
194 } else {
195 dramsize = 0;
196 }
197
198 /* retrieve size of memory connected to SDRAM CS1 */
199 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
200 if (dramsize2 >= 0x13) {
201 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
202 } else {
203 dramsize2 = 0;
204 }
205
206#endif /* CFG_RAMBOOT */
207
208 return dramsize;
209}
210
211#elif defined(CONFIG_MGT5100)
212
213long int initdram (int board_type)
214{
215 ulong dramsize = 0;
216#ifndef CFG_RAMBOOT
217 ulong test1, test2;
218
219 /* setup and enable SDRAM chip selects */
220 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
221 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
222 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
223 __asm__ volatile ("sync");
224
225 /* setup config registers */
226 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
227 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
228
229 /* address select register */
230 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
231 __asm__ volatile ("sync");
232
233 /* find RAM size */
234 sdram_start(0);
235 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
236 sdram_start(1);
237 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
238 if (test1 > test2) {
239 sdram_start(0);
240 dramsize = test1;
241 } else {
242 dramsize = test2;
243 }
244
245 /* set SDRAM end address according to size */
246 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
247
248#else /* CFG_RAMBOOT */
249
250 /* Retrieve amount of SDRAM available */
251 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
252
253#endif /* CFG_RAMBOOT */
254
255 return dramsize;
256}
257
258#else
259#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
260#endif
261
262int checkboard (void)
263{
264#if defined (CONFIG_TQM5200)
265 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
266#endif
267
268#if defined (CONFIG_BC3450)
269 puts ("Dev: GERSYS BC3450\n");
270#endif
271
272 return 0;
273}
274
275void flash_preinit(void)
276{
277 /*
278 * Now, when we are in RAM, enable flash write
279 * access for detection process.
280 * Note that CS_BOOT cannot be cleared when
281 * executing in flash.
282 */
283#if defined(CONFIG_MGT5100)
284 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
285 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
286#endif
287 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
288}
289
290
291#ifdef CONFIG_PCI
292static struct pci_controller hose;
293
294extern void pci_mpc5xxx_init(struct pci_controller *);
295
296void pci_init_board(void)
297{
298 pci_mpc5xxx_init(&hose);
299}
300#endif
301
302#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
303#define GPIO_PSC1_4 0x01000000UL
304
305void init_ide_reset (void)
306{
307 debug ("init_ide_reset\n");
308
309 /* Configure PSC1_4 as GPIO output for ATA reset */
310 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
311 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
312}
313
314void ide_set_reset (int idereset)
315{
316 debug ("ide_reset(%d)\n", idereset);
317
318 if (idereset) {
319 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
320 } else {
321 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
322 }
323}
324#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
325
326#ifdef CONFIG_POST
327/*
328 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
329 * is left open, no keypress is detected.
330 */
331int post_hotkeys_pressed(void)
332{
333 struct mpc5xxx_gpio *gpio;
334
335 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
336
337 /*
338 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
339 * CODEC or UART mode. Consumer IrDA should still be possible.
340 */
341 gpio->port_config &= ~(0x07000000);
342 gpio->port_config |= 0x03000000;
343
344 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
345 gpio->simple_gpioe |= 0x20000000;
346
347 /* Configure GPIO_IRDA_1 as input */
348 gpio->simple_ddr &= ~(0x20000000);
349
350 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
351}
352#endif
353
354#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
355
356void post_word_store (ulong a)
357{
358 volatile ulong *save_addr =
359 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
360
361 *save_addr = a;
362}
363
364ulong post_word_load (void)
365{
366 volatile ulong *save_addr =
367 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
368
369 return *save_addr;
370}
371#endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
372
373
374#ifdef CONFIG_BOARD_EARLY_INIT_R
375int board_early_init_r (void)
376{
377#ifdef CONFIG_RTC_MPC5200
378 struct rtc_time t;
379
380 /* set to Wed Dec 31 19:00:00 1969 */
381 t.tm_sec = t.tm_min = 0;
382 t.tm_hour = 19;
383 t.tm_mday = 31;
384 t.tm_mon = 12;
385 t.tm_year = 1969;
386 t.tm_wday = 3;
387
388 rtc_set(&t);
389#endif /* CONFIG_RTC_MPC5200 */
390
391#ifdef CONFIG_PS2MULT
392 ps2mult_early_init();
393#endif /* CONFIG_PS2MULT */
394 return (0);
395}
396#endif /* CONFIG_BOARD_EARLY_INIT_R */
397
398
399int last_stage_init (void)
400{
401 /*
402 * auto scan for really existing devices and re-set chip select
403 * configuration.
404 */
405 u16 save, tmp;
406 int restore;
407
408 /*
409 * Check for SRAM and SRAM size
410 */
411
412 /* save original SRAM content */
413 save = *(volatile u16 *)CFG_CS2_START;
414 restore = 1;
415
416 /* write test pattern to SRAM */
417 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
418 __asm__ volatile ("sync");
419 /*
420 * Put a different pattern on the data lines: otherwise they may float
421 * long enough to read back what we wrote.
422 */
423 tmp = *(volatile u16 *)CFG_FLASH_BASE;
424 if (tmp == 0xA5A5)
425 puts ("!! possible error in SRAM detection\n");
426
427 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
428 /* no SRAM at all, disable cs */
429 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
430 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
431 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
432 restore = 0;
433 __asm__ volatile ("sync");
434 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
435 /* make sure that we access a mirrored address */
436 *(volatile u16 *)CFG_CS2_START = 0x1111;
437 __asm__ volatile ("sync");
438 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
439 /* SRAM size = 512 kByte */
440 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
441 0x80000);
442 __asm__ volatile ("sync");
443 puts ("SRAM: 512 kB\n");
444 }
445 else
446 puts ("!! possible error in SRAM detection\n");
447 } else {
448 puts ("SRAM: 1 MB\n");
449 }
450 /* restore origianl SRAM content */
451 if (restore) {
452 *(volatile u16 *)CFG_CS2_START = save;
453 __asm__ volatile ("sync");
454 }
455
456 /*
457 * Check for Grafic Controller
458 */
459
460 /* save origianl FB content */
461 save = *(volatile u16 *)CFG_CS1_START;
462 restore = 1;
463
464 /* write test pattern to FB memory */
465 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
466 __asm__ volatile ("sync");
467 /*
468 * Put a different pattern on the data lines: otherwise they may float
469 * long enough to read back what we wrote.
470 */
471 tmp = *(volatile u16 *)CFG_FLASH_BASE;
472 if (tmp == 0xA5A5)
473 puts ("!! possible error in grafic controller detection\n");
474
475 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
476 /* no grafic controller at all, disable cs */
477 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
478 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
479 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
480 restore = 0;
481 __asm__ volatile ("sync");
482 } else {
483 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
484 }
485 /* restore origianl FB content */
486 if (restore) {
487 *(volatile u16 *)CFG_CS1_START = save;
488 __asm__ volatile ("sync");
489 }
490
491 return 0;
492}
493
494#ifdef CONFIG_VIDEO_SM501
495
496#define DISPLAY_WIDTH 640
497#define DISPLAY_HEIGHT 480
498
499#ifdef CONFIG_VIDEO_SM501_8BPP
500#error CONFIG_VIDEO_SM501_8BPP not supported.
501#endif /* CONFIG_VIDEO_SM501_8BPP */
502
503#ifdef CONFIG_VIDEO_SM501_16BPP
504#error CONFIG_VIDEO_SM501_16BPP not supported.
505#endif /* CONFIG_VIDEO_SM501_16BPP */
506
507#ifdef CONFIG_VIDEO_SM501_32BPP
508static const SMI_REGS init_regs [] =
509{
510#if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
511 /* FP only */
512 {0x00004, 0x0},
513 {0x00048, 0x00021807},
514 {0x0004C, 0x091a0a01},
515 {0x00054, 0x1},
516 {0x00040, 0x00021807},
517 {0x00044, 0x091a0a01},
518 {0x00054, 0x0},
519 {0x80000, 0x01013106},
520 {0x80004, 0xc428bb17},
521 {0x80000, 0x03013106},
522 {0x8000C, 0x00000000},
523 {0x80010, 0x0a000a00},
524 {0x80014, 0x02800000},
525 {0x80018, 0x01e00000},
526 {0x8001C, 0x00000000},
527 {0x80020, 0x01e00280},
528 {0x80024, 0x02fa027f},
529 {0x80028, 0x004a028b},
530 {0x8002C, 0x020c01df},
531 {0x80030, 0x000201e9},
532 {0x80200, 0x00010200},
533 {0x80000, 0x0f013106},
534#elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
535 /* CRT only */
536 {0x00004, 0x0},
537 {0x00048, 0x00021807},
538 {0x0004C, 0x10090a01},
539 {0x00054, 0x1},
540 {0x00040, 0x00021807},
541 {0x00044, 0x10090a01},
542 {0x00054, 0x0},
543 {0x80200, 0x00010000},
544 {0x80204, 0x0},
545 {0x80208, 0x0A000A00},
546 {0x8020C, 0x02fa027f},
547 {0x80210, 0x004a028b},
548 {0x80214, 0x020c01df},
549 {0x80218, 0x000201e9},
550 {0x80200, 0x00013306},
551#else /* panel + CRT */
552 {0x00004, 0x0},
553 {0x00048, 0x00021807},
554 {0x0004C, 0x091a0a01},
555 {0x00054, 0x1},
556 {0x00040, 0x00021807},
557 {0x00044, 0x091a0a01},
558 {0x00054, 0x0},
559 {0x80000, 0x0f013106},
560 {0x80004, 0xc428bb17},
561 {0x8000C, 0x00000000},
562 {0x80010, 0x0a000a00},
563 {0x80014, 0x02800000},
564 {0x80018, 0x01e00000},
565 {0x8001C, 0x00000000},
566 {0x80020, 0x01e00280},
567 {0x80024, 0x02fa027f},
568 {0x80028, 0x004a028b},
569 {0x8002C, 0x020c01df},
570 {0x80030, 0x000201e9},
571 {0x80200, 0x00010000},
572#endif
573 {0, 0}
574};
575#endif /* CONFIG_VIDEO_SM501_32BPP */
576
577#ifdef CONFIG_CONSOLE_EXTRA_INFO
578/*
579 * Return text to be printed besides the logo.
580 */
581void video_get_info_str (int line_number, char *info)
582{
583 if (line_number == 1) {
584#if defined (CONFIG_TQM5200)
585 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
586#else
587#error No supported board selected
588#endif /* CONFIG_TQM5200 */
589
590#if defined (CONFIG_BC3450)
591 } else if (line_number == 2) {
592 strcpy (info, " Dev: GERSYS BC3450");
593#endif /* CONFIG_BC3450 */
594 }
595 else {
596 info [0] = '\0';
597 }
598}
599#endif
600
601/*
602 * Returns SM501 register base address. First thing called in the
603 * driver. Checks if SM501 is physically present.
604 */
605unsigned int board_video_init (void)
606{
607 u16 save, tmp;
608 int restore, ret;
609
610 /*
611 * Check for Grafic Controller
612 */
613
614 /* save origianl FB content */
615 save = *(volatile u16 *)CFG_CS1_START;
616 restore = 1;
617
618 /* write test pattern to FB memory */
619 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
620 __asm__ volatile ("sync");
621 /*
622 * Put a different pattern on the data lines: otherwise they may float
623 * long enough to read back what we wrote.
624 */
625 tmp = *(volatile u16 *)CFG_FLASH_BASE;
626 if (tmp == 0xA5A5)
627 puts ("!! possible error in grafic controller detection\n");
628
629 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
630 /* no grafic controller found */
631 restore = 0;
632 ret = 0;
633 } else {
634 ret = SM501_MMIO_BASE;
635 }
636
637 if (restore) {
638 *(volatile u16 *)CFG_CS1_START = save;
639 __asm__ volatile ("sync");
640 }
641 return ret;
642}
643
644/*
645 * Returns SM501 framebuffer address
646 */
647unsigned int board_video_get_fb (void)
648{
649 return SM501_FB_BASE;
650}
651
652/*
653 * Called after initializing the SM501 and before clearing the screen.
654 */
655void board_validate_screen (unsigned int base)
656{
657}
658
659/*
660 * Return a pointer to the initialization sequence.
661 */
662const SMI_REGS *board_get_regs (void)
663{
664 return init_regs;
665}
666
667int board_get_width (void)
668{
669 return DISPLAY_WIDTH;
670}
671
672int board_get_height (void)
673{
674 return DISPLAY_HEIGHT;
675}
676
677#endif /* CONFIG_VIDEO_SM501 */
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