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1 | // SPDX-License-Identifier: GPL-2.0-or-later |
2 | /* | |
3 | * Copyright 2022 Logic PD, Inc dba Beacon EmbeddedWorks | |
4 | * | |
5 | */ | |
6 | ||
d678a59d | 7 | #include <common.h> |
ab53bd43 AF |
8 | #include <hang.h> |
9 | #include <init.h> | |
10 | #include <log.h> | |
11 | #include <spl.h> | |
12 | #include <asm/global_data.h> | |
13 | #include <asm/arch/clock.h> | |
14 | #include <asm/arch/imx8mp_pins.h> | |
15 | #include <asm/arch/sys_proto.h> | |
16 | #include <asm/mach-imx/boot_mode.h> | |
17 | #include <asm/mach-imx/gpio.h> | |
18 | #include <asm/mach-imx/iomux-v3.h> | |
19 | #include <asm/mach-imx/mxc_i2c.h> | |
20 | #include <asm/arch/ddr.h> | |
21 | #include <power/pmic.h> | |
22 | #include <power/pca9450.h> | |
23 | #include <dm/uclass.h> | |
24 | #include <dm/device.h> | |
25 | ||
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
28 | int spl_board_boot_device(enum boot_device boot_dev_spl) | |
29 | { | |
30 | return BOOT_DEVICE_BOOTROM; | |
31 | } | |
32 | ||
33 | void spl_dram_init(void) | |
34 | { | |
35 | ddr_init(&dram_timing); | |
36 | } | |
37 | ||
38 | void spl_board_init(void) | |
39 | { | |
40 | if (IS_ENABLED(CONFIG_FSL_CAAM)) { | |
41 | struct udevice *dev; | |
42 | int ret; | |
43 | ||
44 | ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev); | |
45 | if (ret) | |
46 | printf("Failed to initialize caam_jr: %d\n", ret); | |
47 | } | |
48 | /* | |
49 | * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does | |
50 | * not allow to change it. Should set the clock after PMIC | |
51 | * setting done. Default is 400Mhz (system_pll1_800m with div = 2) | |
52 | * set by ROM for ND VDD_SOC | |
53 | */ | |
54 | if (IS_ENABLED(CONFIG_IMX8M_VDD_SOC_850MV)) { | |
55 | clock_enable(CCGR_GIC, 0); | |
56 | clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); | |
57 | clock_enable(CCGR_GIC, 1); | |
58 | } | |
59 | } | |
60 | ||
61 | #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) | |
62 | int power_init_board(void) | |
63 | { | |
64 | struct udevice *dev; | |
65 | int ret; | |
66 | ||
67 | ret = pmic_get("pmic@25", &dev); | |
68 | if (ret == -ENODEV) { | |
69 | puts("No pmic@25\n"); | |
70 | return 0; | |
71 | } | |
72 | if (ret != 0) | |
73 | return ret; | |
74 | ||
75 | /* BUCKxOUT_DVS0/1 control BUCK123 output */ | |
76 | pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); | |
77 | ||
78 | /* | |
79 | * increase VDD_SOC to typical value 0.95V before first | |
80 | * DRAM access, set DVS1 to 0.85v for suspend. | |
81 | * Enable DVS control through PMIC_STBY_REQ and | |
82 | * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) | |
83 | */ | |
84 | if (CONFIG_IS_ENABLED(IMX8M_VDD_SOC_850MV)) | |
85 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); | |
86 | else | |
87 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); | |
88 | ||
89 | pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); | |
90 | pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); | |
91 | ||
92 | /* Kernel uses OD/OD freq for SOC */ | |
93 | /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ | |
94 | pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); | |
95 | ||
96 | return 0; | |
97 | } | |
98 | #endif | |
99 | ||
100 | #if IS_ENABLED(CONFIG_SPL_LOAD_FIT) | |
101 | int board_fit_config_name_match(const char *name) | |
102 | { | |
103 | /* Just empty function now - can't decide what to choose */ | |
104 | debug("%s: %s\n", __func__, name); | |
105 | ||
106 | return 0; | |
107 | } | |
108 | #endif | |
109 | ||
110 | void board_init_f(ulong dummy) | |
111 | { | |
112 | int ret; | |
113 | ||
114 | arch_cpu_init(); | |
115 | ||
116 | init_uart_clk(1); | |
117 | ||
118 | ret = spl_early_init(); | |
119 | if (ret) { | |
120 | debug("spl_init() failed: %d\n", ret); | |
121 | hang(); | |
122 | } | |
123 | ||
124 | preloader_console_init(); | |
125 | ||
126 | enable_tzc380(); | |
127 | ||
128 | power_init_board(); | |
129 | ||
130 | /* DDR initialization */ | |
131 | spl_dram_init(); | |
132 | } |