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6cb142fa WD |
1 | /* |
2 | * U-boot - ezkit533.c | |
3 | * | |
155fd766 | 4 | * Copyright (c) 2005-2007 Analog Devices Inc. |
6cb142fa WD |
5 | * |
6 | * (C) Copyright 2000-2004 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
155fd766 AL |
24 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
25 | * MA 02110-1301 USA | |
6cb142fa WD |
26 | */ |
27 | ||
28 | #include <common.h> | |
29 | #if defined(CONFIG_MISC_INIT_R) | |
30 | #include "psd4256.h" | |
31 | #endif | |
32 | ||
1218abf1 WD |
33 | DECLARE_GLOBAL_DATA_PTR; |
34 | ||
6cb142fa WD |
35 | int checkboard(void) |
36 | { | |
6cb142fa WD |
37 | printf("Board: ADI BF533 EZ-Kit Lite board\n"); |
38 | printf(" Support: http://blackfin.uclinux.org/\n"); | |
6cb142fa WD |
39 | return 0; |
40 | } | |
41 | ||
9973e3c6 | 42 | phys_size_t initdram(int board_type) |
6cb142fa | 43 | { |
6cb142fa WD |
44 | #ifdef DEBUG |
45 | int brate; | |
46 | char *tmp = getenv("baudrate"); | |
47 | brate = simple_strtoul(tmp, NULL, 16); | |
3f0606ad | 48 | printf("Serial Port initialized with Baud rate = %x\n", brate); |
6cb142fa WD |
49 | printf("SDRAM attributes:\n"); |
50 | printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles" | |
51 | "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n", | |
52 | 3, 3, 6, 2, 3); | |
6d0f6bcf JCPV |
53 | printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE); |
54 | printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20); | |
6cb142fa | 55 | #endif |
6d0f6bcf JCPV |
56 | gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
57 | gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; | |
58 | return CONFIG_SYS_MAX_RAM_SIZE; | |
6cb142fa WD |
59 | } |
60 | ||
61 | #if defined(CONFIG_MISC_INIT_R) | |
62 | /* miscellaneous platform dependent initialisations */ | |
63 | int misc_init_r(void) | |
64 | { | |
3f0606ad | 65 | /* Set direction bits for Video en/decoder reset as output */ |
6d0f6bcf | 66 | *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) = |
3f0606ad AL |
67 | PSDA_VDEC_RST | PSDA_VENC_RST; |
68 | /* Deactivate Video en/decoder reset lines */ | |
6d0f6bcf | 69 | *(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) = |
3f0606ad AL |
70 | PSDA_VDEC_RST | PSDA_VENC_RST; |
71 | ||
72 | return 0; | |
6cb142fa WD |
73 | } |
74 | #endif |