]>
Commit | Line | Data |
---|---|---|
c1393bb3 VPP |
1 | /* |
2 | * Bluegiga APX4 Development Kit | |
3 | * | |
4 | * Copyright (C) 2012 Bluegiga Technologies Oy | |
5 | * | |
6 | * Authors: | |
7 | * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> | |
8 | * Lauri Hintsala <lauri.hintsala@bluegiga.com> | |
9 | * | |
10 | * Based on spl_boot.c: | |
11 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> | |
12 | * on behalf of DENX Software Engineering GmbH | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
c1393bb3 VPP |
15 | */ |
16 | ||
17 | #include <common.h> | |
18 | #include <config.h> | |
19 | #include <asm/gpio.h> | |
20 | #include <asm/io.h> | |
21 | #include <asm/arch/iomux-mx28.h> | |
22 | #include <asm/arch/imx-regs.h> | |
23 | #include <asm/arch/sys_proto.h> | |
24 | ||
25 | #define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) | |
26 | #define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) | |
27 | #define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) | |
28 | #define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) | |
29 | ||
30 | const iomux_cfg_t iomux_setup[] = { | |
31 | /* DUART */ | |
32 | MX28_PAD_PWM0__DUART_RX, | |
33 | MX28_PAD_PWM1__DUART_TX, | |
34 | ||
35 | /* LED */ | |
36 | MX28_PAD_PWM3__GPIO_3_28, | |
37 | ||
38 | /* MMC0 */ | |
39 | MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, | |
40 | MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, | |
41 | MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, | |
42 | MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, | |
43 | MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, | |
44 | MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | | |
45 | (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL), | |
46 | MX28_PAD_SSP0_SCK__SSP0_SCK | | |
47 | (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), | |
48 | ||
49 | /* GPMI NAND */ | |
50 | MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, | |
51 | MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, | |
52 | MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, | |
53 | MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, | |
54 | MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, | |
55 | MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, | |
56 | MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, | |
57 | MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, | |
58 | MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, | |
59 | MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, | |
60 | MX28_PAD_GPMI_RDN__GPMI_RDN | | |
61 | (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), | |
62 | MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, | |
63 | MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, | |
64 | MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, | |
65 | MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, | |
66 | ||
67 | /* FEC0 */ | |
68 | MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, | |
69 | MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, | |
70 | MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, | |
71 | MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, | |
72 | MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, | |
73 | MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, | |
74 | MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, | |
75 | MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, | |
76 | MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, | |
77 | ||
78 | /* I2C */ | |
79 | MX28_PAD_I2C0_SCL__I2C0_SCL, | |
80 | MX28_PAD_I2C0_SDA__I2C0_SDA, | |
81 | ||
82 | /* EMI */ | |
83 | MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, | |
84 | MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, | |
85 | MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, | |
86 | MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, | |
87 | MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, | |
88 | MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, | |
89 | MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, | |
90 | MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, | |
91 | MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, | |
92 | MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, | |
93 | MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, | |
94 | MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, | |
95 | MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, | |
96 | MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, | |
97 | MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, | |
98 | MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, | |
99 | MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, | |
100 | MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, | |
101 | MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, | |
102 | MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, | |
103 | MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, | |
104 | MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, | |
105 | MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, | |
106 | MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, | |
107 | MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, | |
108 | ||
109 | MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, | |
110 | MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, | |
111 | MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, | |
112 | MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, | |
113 | MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, | |
114 | MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, | |
115 | MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, | |
116 | MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, | |
117 | MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, | |
118 | MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, | |
119 | MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, | |
120 | MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, | |
121 | MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, | |
122 | MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, | |
123 | MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, | |
124 | MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, | |
125 | MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, | |
126 | MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, | |
127 | MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, | |
128 | MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, | |
129 | MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, | |
130 | MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, | |
131 | MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, | |
132 | MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, | |
133 | }; | |
134 | ||
135 | void board_init_ll(void) | |
136 | { | |
1e0cf5c3 | 137 | mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); |
c1393bb3 VPP |
138 | |
139 | /* switch LED on */ | |
140 | gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); | |
141 | } | |
142 | ||
1e0cf5c3 | 143 | void mxs_adjust_memory_params(uint32_t *dram_vals) |
c1393bb3 VPP |
144 | { |
145 | /* | |
146 | * All address lines are routed from CPU to memory chip. | |
147 | * ADDR_PINS field is set to zero. | |
148 | */ | |
149 | dram_vals[0x74 >> 2] = 0x0f02000a; | |
150 | ||
151 | /* Used memory has 4 banks. EIGHT_BANK_MODE bit is disabled. */ | |
152 | dram_vals[0x7c >> 2] = 0x00000101; | |
153 | } |