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354bc6fe WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc8xx.h> | |
26 | ||
27 | /* ------------------------------------------------------------------------- */ | |
28 | ||
29 | static long int dram_size (long int, long int *, long int); | |
30 | ||
31 | /* ------------------------------------------------------------------------- */ | |
32 | ||
33 | #define _NOT_USED_ 0xFFFFFFFF | |
34 | ||
35 | const uint sdram_table[] = | |
36 | { | |
37 | /* | |
38 | * Single Read. (Offset 0 in UPMA RAM) | |
39 | */ | |
40 | 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, | |
41 | 0x1FF77C47, /* last */ | |
42 | /* | |
43 | * SDRAM Initialization (offset 5 in UPMA RAM) | |
44 | * | |
45 | * This is no UPM entry point. The following definition uses | |
46 | * the remaining space to establish an initialization | |
47 | * sequence, which is executed by a RUN command. | |
48 | * | |
49 | */ | |
50 | 0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */ | |
51 | /* | |
52 | * Burst Read. (Offset 8 in UPMA RAM) | |
53 | */ | |
54 | 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, | |
55 | 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ | |
56 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
57 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
58 | /* | |
59 | * Single Write. (Offset 18 in UPMA RAM) | |
60 | */ | |
61 | 0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ | |
62 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
63 | /* | |
64 | * Burst Write. (Offset 20 in UPMA RAM) | |
65 | */ | |
66 | 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, | |
67 | 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ | |
68 | _NOT_USED_, | |
69 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
70 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
71 | /* | |
72 | * Refresh (Offset 30 in UPMA RAM) | |
73 | */ | |
74 | 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, | |
75 | 0xFFFFFC84, 0xFFFFFC07, /* last */ | |
76 | _NOT_USED_, _NOT_USED_, | |
77 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
78 | /* | |
79 | * Exception. (Offset 3c in UPMA RAM) | |
80 | */ | |
81 | 0x7FFFFC07, /* last */ | |
82 | _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
83 | }; | |
84 | ||
85 | /* ------------------------------------------------------------------------- */ | |
86 | ||
87 | ||
88 | /* | |
89 | * Check Board Identity: | |
90 | */ | |
91 | ||
92 | int checkboard (void) | |
93 | { | |
77ddac94 | 94 | unsigned char *s = (unsigned char *)getenv ("serial#"); |
354bc6fe WD |
95 | |
96 | puts ("Board: TTTech C2MON "); | |
97 | ||
98 | for (; s && *s; ++s) { | |
99 | if (*s == ' ') | |
100 | break; | |
101 | putc (*s); | |
102 | } | |
103 | ||
104 | putc ('\n'); | |
105 | ||
106 | return (0); | |
107 | } | |
108 | ||
109 | /* ------------------------------------------------------------------------- */ | |
110 | ||
9973e3c6 | 111 | phys_size_t initdram (int board_type) |
354bc6fe | 112 | { |
6d0f6bcf | 113 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
354bc6fe WD |
114 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
115 | unsigned long reg; | |
116 | long int size8, size9; | |
117 | long int size = 0; | |
118 | ||
119 | upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint)); | |
120 | ||
121 | /* | |
122 | * Preliminary prescaler for refresh (depends on number of | |
123 | * banks): This value is selected for four cycles every 62.4 us | |
124 | * with two SDRAM banks or four cycles every 31.2 us with one | |
125 | * bank. It will be adjusted after memory sizing. | |
126 | */ | |
6d0f6bcf | 127 | memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K; |
354bc6fe WD |
128 | |
129 | memctl->memc_mar = 0x00000088; | |
130 | ||
131 | /* | |
132 | * Map controller bank 2 the SDRAM bank 2 at physical address 0. | |
133 | */ | |
6d0f6bcf JCPV |
134 | memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; |
135 | memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; | |
354bc6fe | 136 | |
6d0f6bcf | 137 | memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */ |
354bc6fe WD |
138 | |
139 | udelay (200); | |
140 | ||
141 | /* perform SDRAM initializsation sequence */ | |
142 | ||
143 | memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */ | |
144 | udelay (1); | |
145 | memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */ | |
146 | udelay (1); | |
147 | ||
148 | memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ | |
149 | ||
150 | udelay (1000); | |
151 | ||
152 | /* | |
153 | * Check Bank 0 Memory Size | |
154 | * | |
155 | * try 8 column mode | |
156 | */ | |
6d0f6bcf | 157 | size8 = dram_size (CONFIG_SYS_MAMR_8COL, |
77ddac94 | 158 | SDRAM_BASE2_PRELIM, |
354bc6fe WD |
159 | SDRAM_MAX_SIZE); |
160 | ||
161 | udelay (1000); | |
162 | ||
163 | /* | |
164 | * try 9 column mode | |
165 | */ | |
6d0f6bcf | 166 | size9 = dram_size (CONFIG_SYS_MAMR_9COL, |
77ddac94 | 167 | SDRAM_BASE2_PRELIM, |
354bc6fe WD |
168 | SDRAM_MAX_SIZE); |
169 | ||
170 | if (size8 < size9) { /* leave configuration at 9 columns */ | |
171 | size = size9; | |
172 | /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */ | |
173 | } else { /* back to 8 columns */ | |
174 | size = size8; | |
6d0f6bcf | 175 | memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; |
354bc6fe WD |
176 | udelay (500); |
177 | /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */ | |
178 | } | |
179 | ||
180 | udelay (1000); | |
181 | ||
182 | /* | |
183 | * Adjust refresh rate depending on SDRAM type | |
184 | * For types > 128 MBit leave it at the current (fast) rate | |
185 | */ | |
186 | if (size < 0x02000000) { | |
187 | /* reduce to 15.6 us (62.4 us / quad) */ | |
6d0f6bcf | 188 | memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K; |
354bc6fe WD |
189 | udelay (1000); |
190 | } | |
191 | ||
192 | /* | |
193 | * Final mapping | |
194 | */ | |
6d0f6bcf JCPV |
195 | memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM; |
196 | memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V; | |
354bc6fe WD |
197 | |
198 | /* | |
199 | * No bank 1 | |
200 | * | |
201 | * invalidate bank | |
202 | */ | |
203 | memctl->memc_br3 = 0; | |
204 | ||
205 | /* adjust refresh rate depending on SDRAM type, one bank */ | |
206 | reg = memctl->memc_mptpr; | |
6d0f6bcf | 207 | reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */ |
354bc6fe WD |
208 | memctl->memc_mptpr = reg; |
209 | ||
210 | udelay (10000); | |
211 | ||
212 | return (size); | |
213 | } | |
214 | ||
215 | /* ------------------------------------------------------------------------- */ | |
216 | ||
217 | /* | |
218 | * Check memory range for valid RAM. A simple memory test determines | |
219 | * the actually available RAM size between addresses `base' and | |
220 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
221 | * - short between address lines | |
222 | * - short between data lines | |
223 | */ | |
224 | ||
225 | static long int dram_size (long int mamr_value, long int *base, | |
226 | long int maxsize) | |
227 | { | |
6d0f6bcf | 228 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
354bc6fe | 229 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
354bc6fe WD |
230 | |
231 | memctl->memc_mamr = mamr_value; | |
232 | ||
c83bf6a2 | 233 | return (get_ram_size(base, maxsize)); |
354bc6fe | 234 | } |