[people/ms/u-boot.git] / board / canmb / canmb.c

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m32s2-75.h"
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

phys_size_t initdram(void)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize + dramsize2;
}

int checkboard (void)
{
	puts ("Board: CANMB\n");
	return 0;
}

int board_early_init_r (void)
{
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	*(vu_long *)MPC5XXX_BOOTCS_START =
	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
	*(vu_long *)MPC5XXX_BOOTCS_STOP =
	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
	return 0;
}
Commit	Line	Data
5e5f9ed2 WD	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
b2323ea6 WD	5	* (C) Copyright 2004
b2323ea6 WD	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
5e5f9ed2	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
5e5f9ed2 WD	9	*/
	10
	11	#include <common.h>
	12	#include <mpc5xxx.h>
	13	#include <pci.h>
	14
b2323ea6 WD	15	#if defined(CONFIG_MPC5200_DDR)
	16	#include "mt46v16m16-75.h"
	17	#else
	18	#include "mt48lc16m32s2-75.h"
5e5f9ed2 WD	19	#endif
5e5f9ed2 WD	20
6d0f6bcf	21	#ifndef CONFIG_SYS_RAMBOOT
b2323ea6 WD	22	static void sdram_start (int hi_addr)
	23	{
	24	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
5e5f9ed2 WD	25
5e5f9ed2 WD	26	/* unlock mode register */
b2323ea6 WD	27	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	28	__asm__ volatile ("sync");
	29
5e5f9ed2	30	/* precharge all banks */
b2323ea6 WD	31	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	32	__asm__ volatile ("sync");
	33
	34	#if SDRAM_DDR
	35	/* set mode register: extended mode */
	36	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	37	__asm__ volatile ("sync");
	38
	39	/* set mode register: reset DLL */
	40	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	41	__asm__ volatile ("sync");
5e5f9ed2	42	#endif
b2323ea6	43
5e5f9ed2	44	/* precharge all banks */
b2323ea6 WD	45	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	46	__asm__ volatile ("sync");
	47
5e5f9ed2	48	/* auto refresh */
b2323ea6 WD	49	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	50	__asm__ volatile ("sync");
	51
5e5f9ed2	52	/* set mode register */
b2323ea6 WD	53	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	54	__asm__ volatile ("sync");
	55
5e5f9ed2	56	/* normal operation */
b2323ea6 WD	57	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	58	__asm__ volatile ("sync");
	59	}
	60	#endif
	61
	62	/*
	63	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	64	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
b2323ea6 WD	65	* is something else than 0x00000000.
	66	*/
	67
52c41180	68	phys_size_t initdram(void)
b2323ea6 WD	69	{
	70	ulong dramsize = 0;
	71	ulong dramsize2 = 0;
6d0f6bcf	72	#ifndef CONFIG_SYS_RAMBOOT
b2323ea6 WD	73	ulong test1, test2;
	74
	75	/* setup SDRAM chip selects */
	76	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	77	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	78	__asm__ volatile ("sync");
	79
	80	/* setup config registers */
	81	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	82	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	83	__asm__ volatile ("sync");
	84
	85	#if SDRAM_DDR
	86	/* set tap delay */
	87	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	88	__asm__ volatile ("sync");
	89	#endif
	90
	91	/* find RAM size using SDRAM CS0 only */
	92	sdram_start(0);
ff377b1c	93	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6	94	sdram_start(1);
ff377b1c	95	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6 WD	96	if (test1 > test2) {
	97	sdram_start(0);
	98	dramsize = test1;
	99	} else {
	100	dramsize = test2;
	101	}
	102
	103	/* memory smaller than 1MB is impossible */
	104	if (dramsize < (1 << 20)) {
	105	dramsize = 0;
	106	}
	107
	108	/* set SDRAM CS0 size according to the amount of RAM found */
	109	if (dramsize > 0) {
	110	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	111	} else {
	112	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	113	}
	114
	115	/* let SDRAM CS1 start right after CS0 */
	116	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	117
	118	/* find RAM size using SDRAM CS1 only */
07cc0999	119	if (!dramsize)
a6310928	120	sdram_start(0);
ff377b1c	121	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928 WD	122	if (!dramsize) {
a6310928 WD	123	sdram_start(1);
ff377b1c	124	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928	125	}
b2323ea6 WD	126	if (test1 > test2) {
	127	sdram_start(0);
	128	dramsize2 = test1;
	129	} else {
	130	dramsize2 = test2;
	131	}
	132
	133	/* memory smaller than 1MB is impossible */
	134	if (dramsize2 < (1 << 20)) {
	135	dramsize2 = 0;
	136	}
	137
	138	/* set SDRAM CS1 size according to the amount of RAM found */
	139	if (dramsize2 > 0) {
	140	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	141	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	142	} else {
	143	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	144	}
	145
6d0f6bcf	146	#else /* CONFIG_SYS_RAMBOOT */
b2323ea6 WD	147
	148	/* retrieve size of memory connected to SDRAM CS0 */
	149	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	150	if (dramsize >= 0x13) {
	151	dramsize = (1 << (dramsize - 0x13)) << 20;
	152	} else {
	153	dramsize = 0;
	154	}
	155
	156	/* retrieve size of memory connected to SDRAM CS1 */
	157	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	158	if (dramsize2 >= 0x13) {
	159	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	160	} else {
	161	dramsize2 = 0;
	162	}
5e5f9ed2	163
6d0f6bcf	164	#endif /* CONFIG_SYS_RAMBOOT */
5e5f9ed2	165
b2323ea6 WD	166	return dramsize + dramsize2;
	167	}
	168
5e5f9ed2 WD	169	int checkboard (void)
	170	{
	171	puts ("Board: CANMB\n");
	172	return 0;
	173	}
	174
	175	int board_early_init_r (void)
	176	{
	177	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	178	(vu_long )MPC5XXX_BOOTCS_START =
6d0f6bcf	179	(vu_long )MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
5e5f9ed2	180	(vu_long )MPC5XXX_BOOTCS_STOP =
6d0f6bcf	181	(vu_long )MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
5e5f9ed2 WD	182	return 0;
5e5f9ed2 WD	183	}