[people/ms/u-boot.git] / board / canmb / canmb.c

/*
 * (C) Copyright 2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m32s2-75.h"
#endif

#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 *            is something else than 0x00000000.
 */

#if defined(CONFIG_MPC5200)
phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CONFIG_SYS_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize + dramsize2;
}

#elif defined(CONFIG_MGT5100)

phys_size_t initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* setup and enable SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;

	/* address select register */
	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	__asm__ volatile ("sync");

	/* find RAM size */
	sdram_start(0);
	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* set SDRAM end address according to size */
	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);

#else /* CONFIG_SYS_RAMBOOT */

	/* Retrieve amount of SDRAM available */
	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);

#endif /* CONFIG_SYS_RAMBOOT */

	return dramsize;
}

#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

int checkboard (void)
{
	puts ("Board: CANMB\n");
	return 0;
}

int board_early_init_r (void)
{
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	*(vu_long *)MPC5XXX_BOOTCS_START =
	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
	*(vu_long *)MPC5XXX_BOOTCS_STOP =
	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
	return 0;
}
Commit	Line	Data
5e5f9ed2 WD	1	/*
	2	* (C) Copyright 2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
b2323ea6 WD	5	* (C) Copyright 2004
b2323ea6 WD	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
5e5f9ed2 WD	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
	29	#include <pci.h>
	30
b2323ea6 WD	31	#if defined(CONFIG_MPC5200_DDR)
	32	#include "mt46v16m16-75.h"
	33	#else
	34	#include "mt48lc16m32s2-75.h"
5e5f9ed2 WD	35	#endif
5e5f9ed2 WD	36
6d0f6bcf	37	#ifndef CONFIG_SYS_RAMBOOT
b2323ea6 WD	38	static void sdram_start (int hi_addr)
	39	{
	40	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
5e5f9ed2 WD	41
5e5f9ed2 WD	42	/* unlock mode register */
b2323ea6 WD	43	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	44	__asm__ volatile ("sync");
	45
5e5f9ed2	46	/* precharge all banks */
b2323ea6 WD	47	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	48	__asm__ volatile ("sync");
	49
	50	#if SDRAM_DDR
	51	/* set mode register: extended mode */
	52	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	53	__asm__ volatile ("sync");
	54
	55	/* set mode register: reset DLL */
	56	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	57	__asm__ volatile ("sync");
5e5f9ed2	58	#endif
b2323ea6	59
5e5f9ed2	60	/* precharge all banks */
b2323ea6 WD	61	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	62	__asm__ volatile ("sync");
	63
5e5f9ed2	64	/* auto refresh */
b2323ea6 WD	65	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	66	__asm__ volatile ("sync");
	67
5e5f9ed2	68	/* set mode register */
b2323ea6 WD	69	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	70	__asm__ volatile ("sync");
	71
5e5f9ed2	72	/* normal operation */
b2323ea6 WD	73	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	74	__asm__ volatile ("sync");
	75	}
	76	#endif
	77
	78	/*
	79	* ATTENTION: Although partially referenced initdram does NOT make real use
6d0f6bcf	80	* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
b2323ea6 WD	81	* is something else than 0x00000000.
	82	*/
	83
	84	#if defined(CONFIG_MPC5200)
9973e3c6	85	phys_size_t initdram (int board_type)
b2323ea6 WD	86	{
	87	ulong dramsize = 0;
	88	ulong dramsize2 = 0;
6d0f6bcf	89	#ifndef CONFIG_SYS_RAMBOOT
b2323ea6 WD	90	ulong test1, test2;
	91
	92	/* setup SDRAM chip selects */
	93	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	94	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	95	__asm__ volatile ("sync");
	96
	97	/* setup config registers */
	98	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	99	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	100	__asm__ volatile ("sync");
	101
	102	#if SDRAM_DDR
	103	/* set tap delay */
	104	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	105	__asm__ volatile ("sync");
	106	#endif
	107
	108	/* find RAM size using SDRAM CS0 only */
	109	sdram_start(0);
6d0f6bcf	110	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6	111	sdram_start(1);
6d0f6bcf	112	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6 WD	113	if (test1 > test2) {
	114	sdram_start(0);
	115	dramsize = test1;
	116	} else {
	117	dramsize = test2;
	118	}
	119
	120	/* memory smaller than 1MB is impossible */
	121	if (dramsize < (1 << 20)) {
	122	dramsize = 0;
	123	}
	124
	125	/* set SDRAM CS0 size according to the amount of RAM found */
	126	if (dramsize > 0) {
	127	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	128	} else {
	129	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	130	}
	131
	132	/* let SDRAM CS1 start right after CS0 */
	133	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	134
	135	/* find RAM size using SDRAM CS1 only */
07cc0999	136	if (!dramsize)
a6310928	137	sdram_start(0);
6d0f6bcf	138	test2 = test1 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928 WD	139	if (!dramsize) {
a6310928 WD	140	sdram_start(1);
6d0f6bcf	141	test2 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
a6310928	142	}
b2323ea6 WD	143	if (test1 > test2) {
	144	sdram_start(0);
	145	dramsize2 = test1;
	146	} else {
	147	dramsize2 = test2;
	148	}
	149
	150	/* memory smaller than 1MB is impossible */
	151	if (dramsize2 < (1 << 20)) {
	152	dramsize2 = 0;
	153	}
	154
	155	/* set SDRAM CS1 size according to the amount of RAM found */
	156	if (dramsize2 > 0) {
	157	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	158	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	159	} else {
	160	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	161	}
	162
6d0f6bcf	163	#else /* CONFIG_SYS_RAMBOOT */
b2323ea6 WD	164
	165	/* retrieve size of memory connected to SDRAM CS0 */
	166	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	167	if (dramsize >= 0x13) {
	168	dramsize = (1 << (dramsize - 0x13)) << 20;
	169	} else {
	170	dramsize = 0;
	171	}
	172
	173	/* retrieve size of memory connected to SDRAM CS1 */
	174	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	175	if (dramsize2 >= 0x13) {
	176	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	177	} else {
	178	dramsize2 = 0;
	179	}
5e5f9ed2	180
6d0f6bcf	181	#endif /* CONFIG_SYS_RAMBOOT */
5e5f9ed2	182
b2323ea6 WD	183	return dramsize + dramsize2;
	184	}
	185
	186	#elif defined(CONFIG_MGT5100)
	187
9973e3c6	188	phys_size_t initdram (int board_type)
b2323ea6 WD	189	{
b2323ea6 WD	190	ulong dramsize = 0;
6d0f6bcf	191	#ifndef CONFIG_SYS_RAMBOOT
b2323ea6 WD	192	ulong test1, test2;
	193
	194	/* setup and enable SDRAM chip selects */
	195	(vu_long )MPC5XXX_SDRAM_START = 0x00000000;
	196	(vu_long )MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	197	(vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
	198	__asm__ volatile ("sync");
	199
	200	/* setup config registers */
	201	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	202	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	203
	204	/* address select register */
	205	(vu_long )MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	206	__asm__ volatile ("sync");
	207
	208	/* find RAM size */
	209	sdram_start(0);
6d0f6bcf	210	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6	211	sdram_start(1);
6d0f6bcf	212	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
b2323ea6 WD	213	if (test1 > test2) {
	214	sdram_start(0);
	215	dramsize = test1;
	216	} else {
	217	dramsize = test2;
	218	}
	219
	220	/* set SDRAM end address according to size */
	221	(vu_long )MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
	222
6d0f6bcf	223	#else /* CONFIG_SYS_RAMBOOT */
b2323ea6 WD	224
	225	/* Retrieve amount of SDRAM available */
	226	dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
	227
6d0f6bcf	228	#endif /* CONFIG_SYS_RAMBOOT */
5e5f9ed2	229
5e5f9ed2 WD	230	return dramsize;
	231	}
	232
b2323ea6 WD	233	#else
	234	#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
	235	#endif
	236
5e5f9ed2 WD	237	int checkboard (void)
	238	{
	239	puts ("Board: CANMB\n");
	240	return 0;
	241	}
	242
	243	int board_early_init_r (void)
	244	{
	245	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	246	(vu_long )MPC5XXX_BOOTCS_START =
6d0f6bcf	247	(vu_long )MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
5e5f9ed2	248	(vu_long )MPC5XXX_BOOTCS_STOP =
6d0f6bcf	249	(vu_long )MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
5e5f9ed2 WD	250	return 0;
5e5f9ed2 WD	251	}