]>
Commit | Line | Data |
---|---|---|
8b219cf0 MF |
1 | /* |
2 | * video.c - run splash screen on lcd | |
3 | * | |
4 | * Copyright (c) 2007-2008 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2 or later. | |
7 | */ | |
8 | ||
9 | #include <stdarg.h> | |
10 | #include <common.h> | |
11 | #include <config.h> | |
12 | #include <malloc.h> | |
13 | #include <asm/blackfin.h> | |
14 | #include <asm/mach-common/bits/dma.h> | |
15 | #include <i2c.h> | |
16 | #include <linux/types.h> | |
17 | #include <devices.h> | |
18 | ||
19 | int gunzip(void *, int, unsigned char *, unsigned long *); | |
20 | ||
21 | #ifdef CONFIG_VIDEO | |
22 | ||
23 | #define DMA_SIZE16 2 | |
24 | ||
25 | #include <asm/mach-common/bits/eppi.h> | |
26 | ||
27 | #include <asm/bfin_logo_230x230.h> | |
28 | ||
29 | #define LCD_X_RES 480 /*Horizontal Resolution */ | |
30 | #define LCD_Y_RES 272 /* Vertical Resolution */ | |
31 | ||
32 | #define LCD_BPP 24 /* Bit Per Pixel */ | |
33 | #define LCD_PIXEL_SIZE (LCD_BPP / 8) | |
34 | #define DMA_BUS_SIZE 32 | |
35 | #define ACTIVE_VIDEO_MEM_OFFSET 0 | |
36 | ||
37 | /* -- Horizontal synchronizing -- | |
38 | * | |
39 | * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet | |
40 | * (LCY-W-06602A Page 9 of 22) | |
41 | * | |
42 | * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz | |
43 | * | |
44 | * Period TH - 525 - Clock | |
45 | * Pulse width THp - 41 - Clock | |
46 | * Horizontal period THd - 480 - Clock | |
47 | * Back porch THb - 2 - Clock | |
48 | * Front porch THf - 2 - Clock | |
49 | * | |
50 | * -- Vertical synchronizing -- | |
51 | * Period TV - 286 - Line | |
52 | * Pulse width TVp - 10 - Line | |
53 | * Vertical period TVd - 272 - Line | |
54 | * Back porch TVb - 2 - Line | |
55 | * Front porch TVf - 2 - Line | |
56 | */ | |
57 | ||
58 | #define LCD_CLK (8*1000*1000) /* 8MHz */ | |
59 | ||
60 | /* # active data to transfer after Horizontal Delay clock */ | |
61 | #define EPPI_HCOUNT LCD_X_RES | |
62 | ||
63 | /* # active lines to transfer after Vertical Delay clock */ | |
64 | #define EPPI_VCOUNT LCD_Y_RES | |
65 | ||
66 | /* Samples per Line = 480 (active data) + 45 (padding) */ | |
67 | #define EPPI_LINE 525 | |
68 | ||
69 | /* Lines per Frame = 272 (active data) + 14 (padding) */ | |
70 | #define EPPI_FRAME 286 | |
71 | ||
72 | /* FS1 (Hsync) Width (Typical)*/ | |
73 | #define EPPI_FS1W_HBL 41 | |
74 | ||
75 | /* FS1 (Hsync) Period (Typical) */ | |
76 | #define EPPI_FS1P_AVPL EPPI_LINE | |
77 | ||
78 | /* Horizontal Delay clock after assertion of Hsync (Typical) */ | |
79 | #define EPPI_HDELAY 43 | |
80 | ||
81 | /* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */ | |
82 | #define EPPI_FS2W_LVB (EPPI_LINE * 10) | |
83 | ||
84 | /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */ | |
85 | #define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME) | |
86 | ||
87 | /* Vertical Delay after assertion of Vsync (2 Lines) */ | |
88 | #define EPPI_VDELAY 12 | |
89 | ||
90 | #define EPPI_CLIP 0xFF00FF00 | |
91 | ||
92 | /* EPPI Control register configuration value for RGB out | |
93 | * - EPPI as Output | |
94 | * GP 2 frame sync mode, | |
95 | * Internal Clock generation disabled, Internal FS generation enabled, | |
96 | * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge, | |
97 | * FS1 & FS2 are active high, | |
98 | * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) | |
99 | * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled | |
100 | * Swapping Enabled, | |
101 | * One (DMA) Channel Mode, | |
102 | * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output | |
103 | * Regular watermark - when FIFO is 100% full, | |
104 | * Urgent watermark - when FIFO is 75% full | |
105 | */ | |
106 | ||
107 | #define EPPI_CONTROL (0x20136E2E) | |
108 | ||
109 | static inline u16 get_eppi_clkdiv(u32 target_ppi_clk) | |
110 | { | |
111 | u32 sclk = get_sclk(); | |
112 | ||
113 | /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */ | |
114 | ||
115 | return (((sclk / target_ppi_clk) / 2) - 1); | |
116 | } | |
117 | ||
118 | void Init_PPI(void) | |
119 | { | |
120 | u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK); | |
121 | ||
122 | bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL); | |
123 | bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL); | |
124 | bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB); | |
125 | bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF); | |
126 | bfin_write_EPPI0_CLIP(EPPI_CLIP); | |
127 | ||
128 | bfin_write_EPPI0_FRAME(EPPI_FRAME); | |
129 | bfin_write_EPPI0_LINE(EPPI_LINE); | |
130 | ||
131 | bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT); | |
132 | bfin_write_EPPI0_HDELAY(EPPI_HDELAY); | |
133 | bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT); | |
134 | bfin_write_EPPI0_VDELAY(EPPI_VDELAY); | |
135 | ||
136 | bfin_write_EPPI0_CLKDIV(eppi_clkdiv); | |
137 | ||
138 | /* | |
139 | * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out) | |
140 | * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output | |
141 | */ | |
142 | #if defined(CONFIG_VIDEO_RGB666) | |
143 | bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 | | |
144 | RGB_FMT_EN); | |
145 | #else | |
146 | bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) & | |
147 | ~RGB_FMT_EN); | |
148 | #endif | |
149 | ||
150 | } | |
151 | ||
152 | #define DEB2_URGENT 0x2000 /* DEB2 Urgent */ | |
153 | ||
154 | void Init_DMA(void *dst) | |
155 | { | |
156 | ||
157 | #if defined(CONFIG_DEB_DMA_URGENT) | |
158 | *pEBIU_DDRQUE |= DEB2_URGENT; | |
159 | #endif | |
160 | ||
161 | *pDMA12_START_ADDR = dst; | |
162 | ||
163 | /* X count */ | |
164 | *pDMA12_X_COUNT = (LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE; | |
165 | *pDMA12_X_MODIFY = DMA_BUS_SIZE / 8; | |
166 | ||
167 | /* Y count */ | |
168 | *pDMA12_Y_COUNT = LCD_Y_RES; | |
169 | *pDMA12_Y_MODIFY = DMA_BUS_SIZE / 8; | |
170 | ||
171 | /* DMA Config */ | |
172 | *pDMA12_CONFIG = WDSIZE_32 | /* 32 bit DMA */ | |
173 | DMA2D | /* 2D DMA */ | |
174 | FLOW_AUTO; /* autobuffer mode */ | |
175 | } | |
176 | ||
177 | void Init_Ports(void) | |
178 | { | |
179 | *pPORTF_MUX = 0x00000000; | |
180 | *pPORTF_FER |= 0xFFFF; /* PPI0..15 */ | |
181 | ||
182 | *pPORTG_MUX &= | |
183 | ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | | |
184 | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK); | |
185 | *pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17 */ | |
186 | ||
187 | #if !defined(CONFIG_VIDEO_RGB666) | |
188 | *pPORTD_MUX &= | |
189 | ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | | |
190 | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK); | |
191 | *pPORTD_MUX |= | |
192 | (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | | |
193 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4); | |
194 | *pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23 */ | |
195 | #endif | |
196 | ||
197 | *pPORTE_FER &= ~PE3; /* DISP */ | |
198 | *pPORTE_DIR_SET = PE3; | |
199 | *pPORTE_SET = PE3; | |
200 | ||
201 | } | |
202 | ||
203 | void EnableDMA(void) | |
204 | { | |
205 | *pDMA12_CONFIG |= DMAEN; | |
206 | } | |
207 | ||
208 | void DisableDMA(void) | |
209 | { | |
210 | *pDMA12_CONFIG &= ~DMAEN; | |
211 | } | |
212 | ||
213 | /* enable and disable PPI functions */ | |
214 | void EnablePPI(void) | |
215 | { | |
216 | bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN); | |
217 | } | |
218 | ||
219 | void DisablePPI(void) | |
220 | { | |
221 | bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN); | |
222 | } | |
223 | ||
224 | int video_init(void *dst) | |
225 | { | |
226 | Init_Ports(); | |
227 | Init_DMA(dst); | |
228 | EnableDMA(); | |
229 | Init_PPI(); | |
230 | EnablePPI(); | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) | |
236 | { | |
237 | if (dcache_status()) | |
238 | blackfin_dcache_flush_range(logo->data, | |
239 | logo->data + logo->size); | |
240 | ||
241 | bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); | |
242 | ||
243 | /* Setup destination start address */ | |
244 | bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) | |
245 | + (y * LCD_X_RES * LCD_PIXEL_SIZE)); | |
246 | /* Setup destination xcount */ | |
247 | bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); | |
248 | /* Setup destination xmodify */ | |
249 | bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); | |
250 | ||
251 | /* Setup destination ycount */ | |
252 | bfin_write_MDMA_D0_Y_COUNT(logo->height); | |
253 | /* Setup destination ymodify */ | |
254 | bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + | |
255 | DMA_SIZE16); | |
256 | ||
257 | /* Setup Source start address */ | |
258 | bfin_write_MDMA_S0_START_ADDR(logo->data); | |
259 | /* Setup Source xcount */ | |
260 | bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); | |
261 | /* Setup Source xmodify */ | |
262 | bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); | |
263 | ||
264 | /* Setup Source ycount */ | |
265 | bfin_write_MDMA_S0_Y_COUNT(logo->height); | |
266 | /* Setup Source ymodify */ | |
267 | bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); | |
268 | ||
269 | /* Enable source DMA */ | |
270 | bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); | |
271 | SSYNC(); | |
272 | bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); | |
273 | ||
274 | while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ; | |
275 | ||
276 | bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | |
277 | | DMA_ERR); | |
278 | bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | |
279 | | DMA_ERR); | |
280 | ||
281 | } | |
282 | ||
283 | void video_putc(const char c) | |
284 | { | |
285 | } | |
286 | ||
287 | void video_puts(const char *s) | |
288 | { | |
289 | } | |
290 | ||
291 | int drv_video_init(void) | |
292 | { | |
293 | int error, devices = 1; | |
294 | device_t videodev; | |
295 | ||
296 | u8 *dst; | |
297 | u32 fbmem_size = | |
298 | LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; | |
299 | ||
300 | dst = malloc(fbmem_size); | |
301 | ||
302 | if (dst == NULL) { | |
303 | printf("Failed to alloc FB memory\n"); | |
304 | return -1; | |
305 | } | |
306 | #ifdef EASYLOGO_ENABLE_GZIP | |
307 | unsigned char *data = EASYLOGO_DECOMP_BUFFER; | |
308 | unsigned long src_len = EASYLOGO_ENABLE_GZIP; | |
309 | if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { | |
310 | puts("Failed to decompress logo\n"); | |
311 | free(dst); | |
312 | return -1; | |
313 | } | |
314 | bfin_logo.data = data; | |
315 | #endif | |
316 | ||
317 | memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], | |
318 | fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); | |
319 | ||
320 | dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, | |
321 | (LCD_X_RES - bfin_logo.width) / 2, | |
322 | (LCD_Y_RES - bfin_logo.height) / 2); | |
323 | ||
324 | video_init(dst); /* Video initialization */ | |
325 | ||
326 | memset(&videodev, 0, sizeof(videodev)); | |
327 | ||
328 | strcpy(videodev.name, "video"); | |
329 | videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ | |
330 | videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ | |
331 | videodev.putc = video_putc; /* 'putc' function */ | |
332 | videodev.puts = video_puts; /* 'puts' function */ | |
333 | ||
334 | error = device_register(&videodev); | |
335 | ||
336 | return (error == 0) ? devices : error; | |
337 | } | |
338 | ||
339 | #endif |