[people/ms/u-boot.git] / board / compulab / cm_fx6 / cm_fx6.c

/*
 * Board functions for Compulab CM-FX6 board
 *
 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
 *
 * Author: Nikita Kiryanov <nikita@compulab.co.il>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <fdt_support.h>
#include <sata.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/video.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include "common.h"
#include "../common/eeprom.h"
#include "../common/common.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location cm_fx6_splash_locations[] = {
	{
		.name = "sf",
		.storage = SPLASH_STORAGE_SF,
		.offset = 0x100000,
	},
};

int splash_screen_prepare(void)
{
	return cl_splash_screen_prepare(cm_fx6_splash_locations,
					ARRAY_SIZE(cm_fx6_splash_locations));
}
#endif

#ifdef CONFIG_IMX_HDMI
static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

struct display_info_t const displays[] = {
	{
		.bus	= -1,
		.addr	= 0,
		.pixfmt	= IPU_PIX_FMT_RGB24,
		.detect	= detect_hdmi,
		.enable	= cm_fx6_enable_hdmi,
		.mode	= {
			.name           = "HDMI",
			.refresh        = 60,
			.xres           = 1024,
			.yres           = 768,
			.pixclock       = 40385,
			.left_margin    = 220,
			.right_margin   = 40,
			.upper_margin   = 21,
			.lower_margin   = 7,
			.hsync_len      = 60,
			.vsync_len      = 10,
			.sync           = FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED,
		}
	},
};
size_t display_count = ARRAY_SIZE(displays);

static void cm_fx6_setup_display(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	int reg;

	enable_ipu_clock();
	imx_setup_hdmi();
	reg = __raw_readl(&mxc_ccm->CCGR3);
	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
	writel(reg, &mxc_ccm->CCGR3);
}
#else
static inline void cm_fx6_setup_display(void) {}
#endif /* CONFIG_VIDEO_IPUV3 */

#ifdef CONFIG_DWC_AHSATA
static int cm_fx6_issd_gpios[] = {
	/* The order of the GPIOs in the array is important! */
	CM_FX6_SATA_LDO_EN,
	CM_FX6_SATA_PHY_SLP,
	CM_FX6_SATA_NRSTDLY,
	CM_FX6_SATA_PWREN,
	CM_FX6_SATA_NSTANDBY1,
	CM_FX6_SATA_NSTANDBY2,
};

static void cm_fx6_sata_power(int on)
{
	int i;

	if (!on) { /* tell the iSSD that the power will be removed */
		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
		mdelay(10);
	}

	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
		gpio_direction_output(cm_fx6_issd_gpios[i], on);
		udelay(100);
	}

	if (!on) /* for compatibility lower the power loss interrupt */
		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
}

static iomux_v3_cfg_t const sata_pads[] = {
	/* SATA PWR */
	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* SATA CTRL */
	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static int cm_fx6_setup_issd(void)
{
	int ret, i;

	SETUP_IOMUX_PADS(sata_pads);

	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
		ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
		if (ret)
			return ret;
	}

	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
	if (ret)
		return ret;

	return 0;
}

#define CM_FX6_SATA_INIT_RETRIES	10
int sata_initialize(void)
{
	int err, i;

	/* Make sure this gpio has logical 0 value */
	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	udelay(100);
	cm_fx6_sata_power(1);

	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
		err = setup_sata();
		if (err) {
			printf("SATA setup failed: %d\n", err);
			return err;
		}

		udelay(100);

		err = __sata_initialize();
		if (!err)
			break;

		/* There is no device on the SATA port */
		if (sata_port_status(0, 0) == 0)
			break;

		/* There's a device, but link not established. Retry */
	}

	return err;
}

int sata_stop(void)
{
	__sata_stop();
	cm_fx6_sata_power(0);
	mdelay(250);

	return 0;
}
#else
static int cm_fx6_setup_issd(void) { return 0; }
#endif

#ifdef CONFIG_SYS_I2C_MXC
#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
			PAD_CTL_ODE | PAD_CTL_SRE_FAST)

I2C_PADS(i2c0_pads,
	 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(3, 21),
	 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(3, 28));

I2C_PADS(i2c1_pads,
	 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(4, 12),
	 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(4, 13));

I2C_PADS(i2c2_pads,
	 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(1, 3),
	 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(1, 6));


static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
{
	int ret;

	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
	if (ret)
		printf("Warning: I2C%d setup failed: %d\n", busnum, ret);

	return ret;
}

static int cm_fx6_setup_i2c(void)
{
	int ret = 0, err;

	/* i2c<x>_pads are wierd macro variables; we can't use an array */
	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
	if (err)
		ret = err;
	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
	if (err)
		ret = err;
	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
	if (err)
		ret = err;

	return ret;
}
#else
static int cm_fx6_setup_i2c(void) { return 0; }
#endif

#ifdef CONFIG_USB_EHCI_MX6
#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
#define MX6_USBNC_BASEADDR	0x2184800
#define USBNC_USB_H1_PWR_POL	(1 << 9)

static int cm_fx6_setup_usb_host(void)
{
	int err;

	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
	if (err)
		return err;

	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));

	return 0;
}

static int cm_fx6_setup_usb_otg(void)
{
	int err;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
	if (err) {
		printf("USB OTG pwr gpio request failed: %d\n", err);
		return err;
	}

	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
						MUX_PAD_CTRL(WEAK_PULLDOWN));
	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
	/* disable ext. charger detect, or it'll affect signal quality at dp. */
	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
}

int board_ehci_hcd_init(int port)
{
	int ret;
	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);

	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
	if (port != 1)
		return 0;

	/* Set PWR polarity to match power switch's enable polarity */
	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
	if (ret)
		return ret;

	udelay(10);
	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
	if (ret)
		return ret;

	mdelay(1);

	return 0;
}

int board_ehci_power(int port, int on)
{
	if (port == 0)
		return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);

	return 0;
}
#else
static int cm_fx6_setup_usb_otg(void) { return 0; }
static int cm_fx6_setup_usb_host(void) { return 0; }
#endif

#ifdef CONFIG_FEC_MXC
#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

static int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
	 * which cause ethernet link down/up issue, so disable SmartEEE
	 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= ~(0x1 << 8);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		return phydev->drv->config(phydev);

	return 0;
}

static iomux_v3_cfg_t const enet_pads[] = {
	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
};

static int handle_mac_address(char *env_var, uint eeprom_bus)
{
	unsigned char enetaddr[6];
	int rc;

	rc = eth_getenv_enetaddr(env_var, enetaddr);
	if (rc)
		return 0;

	rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
	if (rc)
		return rc;

	if (!is_valid_ether_addr(enetaddr))
		return -1;

	return eth_setenv_enetaddr(env_var, enetaddr);
}

#define SB_FX6_I2C_EEPROM_BUS	0
#define NO_MAC_ADDR		"No MAC address found for %s\n"
int board_eth_init(bd_t *bis)
{
	int err;

	if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
		printf(NO_MAC_ADDR, "primary NIC");

	if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
		printf(NO_MAC_ADDR, "secondary NIC");

	SETUP_IOMUX_PADS(enet_pads);
	/* phy reset */
	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
	if (err)
		printf("Etnernet NRST gpio request failed: %d\n", err);
	gpio_direction_output(CM_FX6_ENET_NRST, 0);
	udelay(500);
	gpio_set_value(CM_FX6_ENET_NRST, 1);
	enable_enet_clk(1);
	return cpu_eth_init(bis);
}
#endif

#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const nand_pads[] = {
	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static void cm_fx6_setup_gpmi_nand(void)
{
	SETUP_IOMUX_PADS(nand_pads);
	/* Enable clock roots */
	enable_usdhc_clk(1, 3);
	enable_usdhc_clk(1, 4);

	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
			  MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
			  MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
}
#else
static void cm_fx6_setup_gpmi_nand(void) {}
#endif

#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC1_BASE_ADDR},
	{USDHC2_BASE_ADDR},
	{USDHC3_BASE_ADDR},
};

static enum mxc_clock usdhc_clk[3] = {
	MXC_ESDHC_CLK,
	MXC_ESDHC2_CLK,
	MXC_ESDHC3_CLK,
};

int board_mmc_init(bd_t *bis)
{
	int i;

	cm_fx6_set_usdhc_iomux();
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
		usdhc_cfg[i].max_bus_width = 4;
		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		enable_usdhc_clk(1, i);
	}

	return 0;
}
#endif

#ifdef CONFIG_MXC_SPI
int cm_fx6_setup_ecspi(void)
{
	cm_fx6_set_ecspi_iomux();
	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
}
#else
int cm_fx6_setup_ecspi(void) { return 0; }
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	uint8_t enetaddr[6];

	/* MAC addr */
	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
		fdt_find_and_setprop(blob,
				     "/soc/aips-bus@02100000/ethernet@02188000",
				     "local-mac-address", enetaddr, 6, 1);
	}

	if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
		fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
				     enetaddr, 6, 1);
	}

	return 0;
}
#endif

int board_init(void)
{
	int ret;

	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	cm_fx6_setup_gpmi_nand();

	ret = cm_fx6_setup_ecspi();
	if (ret)
		printf("Warning: ECSPI setup failed: %d\n", ret);

	ret = cm_fx6_setup_usb_otg();
	if (ret)
		printf("Warning: USB OTG setup failed: %d\n", ret);

	ret = cm_fx6_setup_usb_host();
	if (ret)
		printf("Warning: USB host setup failed: %d\n", ret);

	/*
	 * cm-fx6 may have iSSD not assembled and in this case it has
	 * bypasses for a (m)SATA socket on the baseboard. The socketed
	 * device is not controlled by those GPIOs. So just print a warning
	 * if the setup fails.
	 */
	ret = cm_fx6_setup_issd();
	if (ret)
		printf("Warning: iSSD setup failed: %d\n", ret);

	/* Warn on failure but do not abort boot */
	ret = cm_fx6_setup_i2c();
	if (ret)
		printf("Warning: I2C setup failed: %d\n", ret);

	cm_fx6_setup_display();

	return 0;
}

int checkboard(void)
{
	puts("Board: CM-FX6\n");
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

	switch (gd->ram_size) {
	case 0x10000000: /* DDR_16BIT_256MB */
		gd->bd->bi_dram[0].size = 0x10000000;
		gd->bd->bi_dram[1].size = 0;
		break;
	case 0x20000000: /* DDR_32BIT_512MB */
		gd->bd->bi_dram[0].size = 0x20000000;
		gd->bd->bi_dram[1].size = 0;
		break;
	case 0x40000000:
		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
			gd->bd->bi_dram[0].size = 0x20000000;
			gd->bd->bi_dram[1].size = 0x20000000;
		} else { /* DDR_64BIT_1GB */
			gd->bd->bi_dram[0].size = 0x40000000;
			gd->bd->bi_dram[1].size = 0;
		}
		break;
	case 0x80000000: /* DDR_64BIT_2GB */
		gd->bd->bi_dram[0].size = 0x40000000;
		gd->bd->bi_dram[1].size = 0x40000000;
		break;
	case 0xEFF00000: /* DDR_64BIT_4GB */
		gd->bd->bi_dram[0].size = 0x70000000;
		gd->bd->bi_dram[1].size = 0x7FF00000;
		break;
	}
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	switch (gd->ram_size) {
	case 0x10000000:
	case 0x20000000:
	case 0x40000000:
	case 0x80000000:
		break;
	case 0xF0000000:
		gd->ram_size -= 0x100000;
		break;
	default:
		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
		return -1;
	}

	return 0;
}

u32 get_board_rev(void)
{
	return cl_eeprom_get_board_rev();
}

static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
	.reg = (struct mxc_uart *)UART4_BASE,
};

U_BOOT_DEVICE(cm_fx6_serial) = {
	.name	= "serial_mxc",
	.platdata = &cm_fx6_mxc_serial_plat,
};
Commit	Line	Data
e32028a7 NK	1	/*
	2	* Board functions for Compulab CM-FX6 board
	3	*
	4	* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
	5	*
	6	* Author: Nikita Kiryanov <nikita@compulab.co.il>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
3f0e935f	12	#include <dm.h>
e32028a7	13	#include <fsl_esdhc.h>
02b1343e NK	14	#include <miiphy.h>
	15	#include <netdev.h>
	16	#include <fdt_support.h>
206f38f7	17	#include <sata.h>
a6b0652b	18	#include <asm/arch/crm_regs.h>
e32028a7	19	#include <asm/arch/sys_proto.h>
0f3effb9	20	#include <asm/arch/iomux.h>
deb94d61	21	#include <asm/arch/mxc_hdmi.h>
f42b2f60	22	#include <asm/imx-common/mxc_i2c.h>
206f38f7	23	#include <asm/imx-common/sata.h>
deb94d61	24	#include <asm/imx-common/video.h>
a6b0652b	25	#include <asm/io.h>
02b1343e	26	#include <asm/gpio.h>
86256b79	27	#include <dm/platform_data/serial_mxc.h>
e32028a7	28	#include "common.h"
f66113c0	29	#include "../common/eeprom.h"
3a236a35	30	#include "../common/common.h"
e32028a7 NK	31
	32	DECLARE_GLOBAL_DATA_PTR;
	33
3a236a35 NK	34	#ifdef CONFIG_SPLASH_SCREEN
	35	static struct splash_location cm_fx6_splash_locations[] = {
	36	{
	37	.name = "sf",
	38	.storage = SPLASH_STORAGE_SF,
	39	.offset = 0x100000,
	40	},
	41	};
	42
	43	int splash_screen_prepare(void)
	44	{
	45	return cl_splash_screen_prepare(cm_fx6_splash_locations,
	46	ARRAY_SIZE(cm_fx6_splash_locations));
	47	}
	48	#endif
	49
deb94d61 NK	50	#ifdef CONFIG_IMX_HDMI
	51	static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
	52	{
	53	imx_enable_hdmi_phy();
	54	}
	55
	56	struct display_info_t const displays[] = {
	57	{
	58	.bus = -1,
	59	.addr = 0,
	60	.pixfmt = IPU_PIX_FMT_RGB24,
	61	.detect = detect_hdmi,
	62	.enable = cm_fx6_enable_hdmi,
	63	.mode = {
	64	.name = "HDMI",
	65	.refresh = 60,
	66	.xres = 1024,
	67	.yres = 768,
	68	.pixclock = 40385,
	69	.left_margin = 220,
	70	.right_margin = 40,
	71	.upper_margin = 21,
	72	.lower_margin = 7,
	73	.hsync_len = 60,
	74	.vsync_len = 10,
	75	.sync = FB_SYNC_EXT,
	76	.vmode = FB_VMODE_NONINTERLACED,
	77	}
	78	},
	79	};
	80	size_t display_count = ARRAY_SIZE(displays);
	81
	82	static void cm_fx6_setup_display(void)
	83	{
	84	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	85	int reg;
	86
	87	enable_ipu_clock();
	88	imx_setup_hdmi();
	89	reg = __raw_readl(&mxc_ccm->CCGR3);
	90	reg \|= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK;
	91	writel(reg, &mxc_ccm->CCGR3);
	92	}
	93	#else
	94	static inline void cm_fx6_setup_display(void) {}
	95	#endif /* CONFIG_VIDEO_IPUV3 */
	96
206f38f7 NK	97	#ifdef CONFIG_DWC_AHSATA
	98	static int cm_fx6_issd_gpios[] = {
	99	/* The order of the GPIOs in the array is important! */
b65cbab1	100	CM_FX6_SATA_LDO_EN,
206f38f7 NK	101	CM_FX6_SATA_PHY_SLP,
	102	CM_FX6_SATA_NRSTDLY,
	103	CM_FX6_SATA_PWREN,
	104	CM_FX6_SATA_NSTANDBY1,
	105	CM_FX6_SATA_NSTANDBY2,
206f38f7 NK	106	};
	107
	108	static void cm_fx6_sata_power(int on)
	109	{
	110	int i;
	111
	112	if (!on) { /* tell the iSSD that the power will be removed */
	113	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
	114	mdelay(10);
	115	}
	116
	117	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
	118	gpio_direction_output(cm_fx6_issd_gpios[i], on);
	119	udelay(100);
	120	}
	121
	122	if (!on) /* for compatibility lower the power loss interrupt */
	123	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	124	}
	125
	126	static iomux_v3_cfg_t const sata_pads[] = {
	127	/* SATA PWR */
	128	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	129	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	130	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	131	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	132	/* SATA CTRL */
	133	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	134	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	135	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	136	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	137	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	138	};
	139
8f488c1b	140	static int cm_fx6_setup_issd(void)
206f38f7	141	{
8f488c1b NK	142	int ret, i;
8f488c1b NK	143
206f38f7	144	SETUP_IOMUX_PADS(sata_pads);
206f38f7	145
8f488c1b NK	146	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
	147	ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
	148	if (ret)
	149	return ret;
	150	}
	151
	152	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
	153	if (ret)
	154	return ret;
	155
	156	return 0;
206f38f7 NK	157	}
	158
	159	#define CM_FX6_SATA_INIT_RETRIES 10
	160	int sata_initialize(void)
	161	{
	162	int err, i;
	163
8f488c1b NK	164	/* Make sure this gpio has logical 0 value */
	165	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	166	udelay(100);
8f488c1b NK	167	cm_fx6_sata_power(1);
8f488c1b NK	168
206f38f7 NK	169	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
	170	err = setup_sata();
	171	if (err) {
	172	printf("SATA setup failed: %d\n", err);
	173	return err;
	174	}
	175
	176	udelay(100);
	177
	178	err = __sata_initialize();
	179	if (!err)
	180	break;
	181
	182	/* There is no device on the SATA port */
	183	if (sata_port_status(0, 0) == 0)
	184	break;
	185
	186	/* There's a device, but link not established. Retry */
	187	}
	188
	189	return err;
	190	}
9cad3544 NK	191
	192	int sata_stop(void)
	193	{
	194	__sata_stop();
	195	cm_fx6_sata_power(0);
	196	mdelay(250);
	197
	198	return 0;
	199	}
8f488c1b NK	200	#else
8f488c1b NK	201	static int cm_fx6_setup_issd(void) { return 0; }
206f38f7 NK	202	#endif
206f38f7 NK	203
f42b2f60 NK	204	#ifdef CONFIG_SYS_I2C_MXC
	205	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	206	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	207	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	208
	209	I2C_PADS(i2c0_pads,
	210	PAD_EIM_D21__I2C1_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	211	PAD_EIM_D21__GPIO3_IO21 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	212	IMX_GPIO_NR(3, 21),
	213	PAD_EIM_D28__I2C1_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	214	PAD_EIM_D28__GPIO3_IO28 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	215	IMX_GPIO_NR(3, 28));
	216
	217	I2C_PADS(i2c1_pads,
	218	PAD_KEY_COL3__I2C2_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	219	PAD_KEY_COL3__GPIO4_IO12 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	220	IMX_GPIO_NR(4, 12),
	221	PAD_KEY_ROW3__I2C2_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	222	PAD_KEY_ROW3__GPIO4_IO13 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	223	IMX_GPIO_NR(4, 13));
	224
	225	I2C_PADS(i2c2_pads,
	226	PAD_GPIO_3__I2C3_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	227	PAD_GPIO_3__GPIO1_IO03 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	228	IMX_GPIO_NR(1, 3),
	229	PAD_GPIO_6__I2C3_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	230	PAD_GPIO_6__GPIO1_IO06 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	231	IMX_GPIO_NR(1, 6));
	232
	233
edbf8b4f	234	static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
f42b2f60	235	{
edbf8b4f SG	236	int ret;
	237
	238	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
	239	if (ret)
	240	printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
	241
	242	return ret;
	243	}
	244
	245	static int cm_fx6_setup_i2c(void)
	246	{
	247	int ret = 0, err;
	248
	249	/* i2c<x>_pads are wierd macro variables; we can't use an array */
	250	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
	251	if (err)
	252	ret = err;
	253	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
	254	if (err)
	255	ret = err;
	256	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
	257	if (err)
	258	ret = err;
	259
	260	return ret;
f42b2f60 NK	261	}
f42b2f60 NK	262	#else
edbf8b4f	263	static int cm_fx6_setup_i2c(void) { return 0; }
f42b2f60 NK	264	#endif
f42b2f60 NK	265
0f3effb9 NK	266	#ifdef CONFIG_USB_EHCI_MX6
	267	#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN \| \
	268	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	269	PAD_CTL_HYS \| PAD_CTL_SRE_SLOW)
8f488c1b NK	270	#define MX6_USBNC_BASEADDR 0x2184800
8f488c1b NK	271	#define USBNC_USB_H1_PWR_POL (1 << 9)
0f3effb9	272
8f488c1b	273	static int cm_fx6_setup_usb_host(void)
0f3effb9 NK	274	{
	275	int err;
	276
	277	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
8f488c1b NK	278	if (err)
8f488c1b NK	279	return err;
0f3effb9	280
8f488c1b	281	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9	282	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 \| MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9 NK	283
	284	return 0;
	285	}
	286
8f488c1b	287	static int cm_fx6_setup_usb_otg(void)
0f3effb9	288	{
8f488c1b	289	int err;
0f3effb9 NK	290	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
0f3effb9 NK	291
8f488c1b NK	292	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
	293	if (err) {
	294	printf("USB OTG pwr gpio request failed: %d\n", err);
	295	return err;
0f3effb9 NK	296	}
	297
	298	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(NO_PAD_CTRL));
	299	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID \|
	300	MUX_PAD_CTRL(WEAK_PULLDOWN));
	301	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
	302	/* disable ext. charger detect, or it'll affect signal quality at dp. */
	303	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
	304	}
	305
0f3effb9 NK	306	int board_ehci_hcd_init(int port)
0f3effb9 NK	307	{
8f488c1b	308	int ret;
0f3effb9 NK	309	u32 usbnc_usb_uh1_ctrl = (u32 )(MX6_USBNC_BASEADDR + 4);
0f3effb9 NK	310
8f488c1b NK	311	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
	312	if (port != 1)
	313	return 0;
	314
	315	/* Set PWR polarity to match power switch's enable polarity */
	316	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
	317	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
	318	if (ret)
	319	return ret;
	320
	321	udelay(10);
	322	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
	323	if (ret)
	324	return ret;
	325
	326	mdelay(1);
0f3effb9 NK	327
	328	return 0;
	329	}
	330
	331	int board_ehci_power(int port, int on)
	332	{
	333	if (port == 0)
	334	return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
	335
	336	return 0;
	337	}
8f488c1b NK	338	#else
	339	static int cm_fx6_setup_usb_otg(void) { return 0; }
	340	static int cm_fx6_setup_usb_host(void) { return 0; }
0f3effb9 NK	341	#endif
0f3effb9 NK	342
02b1343e NK	343	#ifdef CONFIG_FEC_MXC
	344	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	345	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	346
	347	static int mx6_rgmii_rework(struct phy_device *phydev)
	348	{
	349	unsigned short val;
	350
	351	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
	352	* which cause ethernet link down/up issue, so disable SmartEEE
	353	*/
	354	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
	355	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
	356	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
	357	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	358	val &= ~(0x1 << 8);
	359	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	360
	361	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	362	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	363	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	364	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	365
	366	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	367	val &= 0xffe3;
	368	val \|= 0x18;
	369	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	370
	371	/* introduce tx clock delay */
	372	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	373	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	374	val \|= 0x0100;
	375	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	376
	377	return 0;
	378	}
	379
	380	int board_phy_config(struct phy_device *phydev)
	381	{
	382	mx6_rgmii_rework(phydev);
	383
	384	if (phydev->drv->config)
	385	return phydev->drv->config(phydev);
	386
	387	return 0;
	388	}
	389
	390	static iomux_v3_cfg_t const enet_pads[] = {
	391	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	392	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	393	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	394	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	395	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	396	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	397	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	398	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	399	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	400	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	401	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	402	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	403	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	404	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	405	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 \| MUX_PAD_CTRL(0x84)),
	406	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \|
407	MUX_PAD_CTRL(ENET_PAD_CTRL)),
408	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \|
409	MUX_PAD_CTRL(ENET_PAD_CTRL)),
410	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \|
411	MUX_PAD_CTRL(ENET_PAD_CTRL)),
412	};
413
eab29802	414	static int handle_mac_address(char *env_var, uint eeprom_bus)
f66113c0 NK	415	{
	416	unsigned char enetaddr[6];
	417	int rc;
	418
eab29802	419	rc = eth_getenv_enetaddr(env_var, enetaddr);
f66113c0 NK	420	if (rc)
	421	return 0;
	422
eab29802	423	rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
f66113c0 NK	424	if (rc)
	425	return rc;
	426
	427	if (!is_valid_ether_addr(enetaddr))
	428	return -1;
	429
eab29802	430	return eth_setenv_enetaddr(env_var, enetaddr);
f66113c0 NK	431	}
f66113c0 NK	432
eab29802 NK	433	#define SB_FX6_I2C_EEPROM_BUS 0
eab29802 NK	434	#define NO_MAC_ADDR "No MAC address found for %s\n"
02b1343e NK	435	int board_eth_init(bd_t *bis)
02b1343e NK	436	{
8f488c1b NK	437	int err;
8f488c1b NK	438
eab29802 NK	439	if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
	440	printf(NO_MAC_ADDR, "primary NIC");
	441
	442	if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
	443	printf(NO_MAC_ADDR, "secondary NIC");
f66113c0	444
02b1343e NK	445	SETUP_IOMUX_PADS(enet_pads);
02b1343e NK	446	/* phy reset */
8f488c1b NK	447	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
	448	if (err)
	449	printf("Etnernet NRST gpio request failed: %d\n", err);
02b1343e NK	450	gpio_direction_output(CM_FX6_ENET_NRST, 0);
	451	udelay(500);
	452	gpio_set_value(CM_FX6_ENET_NRST, 1);
	453	enable_enet_clk(1);
	454	return cpu_eth_init(bis);
	455	}
	456	#endif
	457
a6b0652b NK	458	#ifdef CONFIG_NAND_MXS
	459	static iomux_v3_cfg_t const nand_pads[] = {
	460	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	461	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	462	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	463	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	464	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	465	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	466	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	467	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	468	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	469	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	470	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	471	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	472	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	473	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	474	};
	475
	476	static void cm_fx6_setup_gpmi_nand(void)
	477	{
	478	SETUP_IOMUX_PADS(nand_pads);
	479	/* Enable clock roots */
	480	enable_usdhc_clk(1, 3);
	481	enable_usdhc_clk(1, 4);
	482
	483	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) \|
	484	MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) \|
	485	MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
	486	}
	487	#else
	488	static void cm_fx6_setup_gpmi_nand(void) {}
	489	#endif
	490
e32028a7 NK	491	#ifdef CONFIG_FSL_ESDHC
	492	static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	493	{USDHC1_BASE_ADDR},
	494	{USDHC2_BASE_ADDR},
	495	{USDHC3_BASE_ADDR},
	496	};
	497
	498	static enum mxc_clock usdhc_clk[3] = {
	499	MXC_ESDHC_CLK,
	500	MXC_ESDHC2_CLK,
	501	MXC_ESDHC3_CLK,
	502	};
	503
	504	int board_mmc_init(bd_t *bis)
	505	{
	506	int i;
	507
	508	cm_fx6_set_usdhc_iomux();
	509	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	510	usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
	511	usdhc_cfg[i].max_bus_width = 4;
	512	fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	513	enable_usdhc_clk(1, i);
	514	}
	515
	516	return 0;
	517	}
	518	#endif
	519
8f488c1b NK	520	#ifdef CONFIG_MXC_SPI
	521	int cm_fx6_setup_ecspi(void)
	522	{
	523	cm_fx6_set_ecspi_iomux();
	524	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
	525	}
	526	#else
	527	int cm_fx6_setup_ecspi(void) { return 0; }
	528	#endif
	529
02b1343e	530	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	531	int ft_board_setup(void blob, bd_t bd)
02b1343e NK	532	{
	533	uint8_t enetaddr[6];
	534
	535	/* MAC addr */
	536	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
cc67f4a6 NK	537	fdt_find_and_setprop(blob,
	538	"/soc/aips-bus@02100000/ethernet@02188000",
	539	"local-mac-address", enetaddr, 6, 1);
02b1343e	540	}
e895a4b0	541
eab29802 NK	542	if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
	543	fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
	544	enetaddr, 6, 1);
	545	}
	546
e895a4b0	547	return 0;
02b1343e NK	548	}
	549	#endif
	550
e32028a7 NK	551	int board_init(void)
e32028a7 NK	552	{
edbf8b4f SG	553	int ret;
edbf8b4f SG	554
e32028a7	555	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
a6b0652b	556	cm_fx6_setup_gpmi_nand();
edbf8b4f	557
8f488c1b NK	558	ret = cm_fx6_setup_ecspi();
	559	if (ret)
	560	printf("Warning: ECSPI setup failed: %d\n", ret);
	561
	562	ret = cm_fx6_setup_usb_otg();
	563	if (ret)
	564	printf("Warning: USB OTG setup failed: %d\n", ret);
	565
	566	ret = cm_fx6_setup_usb_host();
	567	if (ret)
	568	printf("Warning: USB host setup failed: %d\n", ret);
	569
	570	/*
	571	* cm-fx6 may have iSSD not assembled and in this case it has
	572	* bypasses for a (m)SATA socket on the baseboard. The socketed
	573	* device is not controlled by those GPIOs. So just print a warning
	574	* if the setup fails.
	575	*/
	576	ret = cm_fx6_setup_issd();
	577	if (ret)
	578	printf("Warning: iSSD setup failed: %d\n", ret);
	579
edbf8b4f SG	580	/* Warn on failure but do not abort boot */
	581	ret = cm_fx6_setup_i2c();
	582	if (ret)
	583	printf("Warning: I2C setup failed: %d\n", ret);
a6b0652b	584
deb94d61 NK	585	cm_fx6_setup_display();
deb94d61 NK	586
e32028a7 NK	587	return 0;
	588	}
	589
	590	int checkboard(void)
	591	{
	592	puts("Board: CM-FX6\n");
	593	return 0;
	594	}
	595
	596	void dram_init_banksize(void)
	597	{
	598	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	599	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	600
	601	switch (gd->ram_size) {
	602	case 0x10000000: /* DDR_16BIT_256MB */
	603	gd->bd->bi_dram[0].size = 0x10000000;
	604	gd->bd->bi_dram[1].size = 0;
	605	break;
	606	case 0x20000000: /* DDR_32BIT_512MB */
	607	gd->bd->bi_dram[0].size = 0x20000000;
	608	gd->bd->bi_dram[1].size = 0;
	609	break;
	610	case 0x40000000:
	611	if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
	612	gd->bd->bi_dram[0].size = 0x20000000;
	613	gd->bd->bi_dram[1].size = 0x20000000;
	614	} else { /* DDR_64BIT_1GB */
	615	gd->bd->bi_dram[0].size = 0x40000000;
	616	gd->bd->bi_dram[1].size = 0;
	617	}
	618	break;
	619	case 0x80000000: /* DDR_64BIT_2GB */
	620	gd->bd->bi_dram[0].size = 0x40000000;
	621	gd->bd->bi_dram[1].size = 0x40000000;
	622	break;
	623	case 0xEFF00000: /* DDR_64BIT_4GB */
	624	gd->bd->bi_dram[0].size = 0x70000000;
	625	gd->bd->bi_dram[1].size = 0x7FF00000;
	626	break;
	627	}
	628	}
	629
	630	int dram_init(void)
	631	{
	632	gd->ram_size = imx_ddr_size();
	633	switch (gd->ram_size) {
	634	case 0x10000000:
	635	case 0x20000000:
	636	case 0x40000000:
	637	case 0x80000000:
	638	break;
	639	case 0xF0000000:
	640	gd->ram_size -= 0x100000;
	641	break;
	642	default:
	643	printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
	644	return -1;
	645	}
	646
	647	return 0;
	648	}
f66113c0 NK	649
	650	u32 get_board_rev(void)
	651	{
	652	return cl_eeprom_get_board_rev();
	653	}
	654
3f0e935f SG	655	static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
	656	.reg = (struct mxc_uart *)UART4_BASE,
	657	};
	658
	659	U_BOOT_DEVICE(cm_fx6_serial) = {
	660	.name = "serial_mxc",
	661	.platdata = &cm_fx6_mxc_serial_plat,
	662	};