[people/ms/u-boot.git] / board / compulab / cm_fx6 / cm_fx6.c

/*
 * Board functions for Compulab CM-FX6 board
 *
 * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
 *
 * Author: Nikita Kiryanov <nikita@compulab.co.il>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <errno.h>
#include <usb.h>
#include <fdt_support.h>
#include <sata.h>
#include <splash.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/sata.h>
#include <asm/imx-common/video.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm/platform_data/serial_mxc.h>
#include "common.h"
#include "../common/eeprom.h"
#include "../common/common.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location cm_fx6_splash_locations[] = {
	{
		.name = "sf",
		.storage = SPLASH_STORAGE_SF,
		.offset = 0x100000,
	},
};

int splash_screen_prepare(void)
{
	return splash_source_load(cm_fx6_splash_locations,
				  ARRAY_SIZE(cm_fx6_splash_locations));
}
#endif

#ifdef CONFIG_IMX_HDMI
static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	imx_setup_hdmi();
	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
	imx_enable_hdmi_phy();
}

static struct display_info_t preset_hdmi_1024X768 = {
	.bus	= -1,
	.addr	= 0,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.enable	= cm_fx6_enable_hdmi,
	.mode	= {
		.name           = "HDMI",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 40385,
		.left_margin    = 220,
		.right_margin   = 40,
		.upper_margin   = 21,
		.lower_margin   = 7,
		.hsync_len      = 60,
		.vsync_len      = 10,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED,
	}
};

static void cm_fx6_setup_display(void)
{
	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	enable_ipu_clock();
	clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
}

int board_video_skip(void)
{
	int ret;
	struct display_info_t *preset;
	char const *panel = getenv("displaytype");

	if (!panel) /* Also accept panel for backward compatibility */
		panel = getenv("panel");

	if (!panel)
		return -ENOENT;

	if (!strcmp(panel, "HDMI"))
		preset = &preset_hdmi_1024X768;
	else
		return -EINVAL;

	ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
	if (ret) {
		printf("Can't init display %s: %d\n", preset->mode.name, ret);
		return ret;
	}

	preset->enable(preset);
	printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
	       preset->mode.yres);

	return 0;
}
#else
static inline void cm_fx6_setup_display(void) {}
#endif /* CONFIG_VIDEO_IPUV3 */

#ifdef CONFIG_DWC_AHSATA
static int cm_fx6_issd_gpios[] = {
	/* The order of the GPIOs in the array is important! */
	CM_FX6_SATA_LDO_EN,
	CM_FX6_SATA_PHY_SLP,
	CM_FX6_SATA_NRSTDLY,
	CM_FX6_SATA_PWREN,
	CM_FX6_SATA_NSTANDBY1,
	CM_FX6_SATA_NSTANDBY2,
};

static void cm_fx6_sata_power(int on)
{
	int i;

	if (!on) { /* tell the iSSD that the power will be removed */
		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
		mdelay(10);
	}

	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
		gpio_direction_output(cm_fx6_issd_gpios[i], on);
		udelay(100);
	}

	if (!on) /* for compatibility lower the power loss interrupt */
		gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
}

static iomux_v3_cfg_t const sata_pads[] = {
	/* SATA PWR */
	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	/* SATA CTRL */
	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static int cm_fx6_setup_issd(void)
{
	int ret, i;

	SETUP_IOMUX_PADS(sata_pads);

	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
		ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
		if (ret)
			return ret;
	}

	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
	if (ret)
		return ret;

	return 0;
}

#define CM_FX6_SATA_INIT_RETRIES	10
int sata_initialize(void)
{
	int err, i;

	/* Make sure this gpio has logical 0 value */
	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	udelay(100);
	cm_fx6_sata_power(1);

	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
		err = setup_sata();
		if (err) {
			printf("SATA setup failed: %d\n", err);
			return err;
		}

		udelay(100);

		err = __sata_initialize();
		if (!err)
			break;

		/* There is no device on the SATA port */
		if (sata_port_status(0, 0) == 0)
			break;

		/* There's a device, but link not established. Retry */
	}

	return err;
}

int sata_stop(void)
{
	__sata_stop();
	cm_fx6_sata_power(0);
	mdelay(250);

	return 0;
}
#else
static int cm_fx6_setup_issd(void) { return 0; }
#endif

#ifdef CONFIG_SYS_I2C_MXC
#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
			PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
			PAD_CTL_ODE | PAD_CTL_SRE_FAST)

I2C_PADS(i2c0_pads,
	 PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(3, 21),
	 PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(3, 28));

I2C_PADS(i2c1_pads,
	 PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(4, 12),
	 PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(4, 13));

I2C_PADS(i2c2_pads,
	 PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(1, 3),
	 PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
	 IMX_GPIO_NR(1, 6));


static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
{
	int ret;

	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
	if (ret)
		printf("Warning: I2C%d setup failed: %d\n", busnum, ret);

	return ret;
}

static int cm_fx6_setup_i2c(void)
{
	int ret = 0, err;

	/* i2c<x>_pads are wierd macro variables; we can't use an array */
	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
	if (err)
		ret = err;
	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
	if (err)
		ret = err;
	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
	if (err)
		ret = err;

	return ret;
}
#else
static int cm_fx6_setup_i2c(void) { return 0; }
#endif

#ifdef CONFIG_USB_EHCI_MX6
#define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
			PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
			PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
#define MX6_USBNC_BASEADDR	0x2184800
#define USBNC_USB_H1_PWR_POL	(1 << 9)

static int cm_fx6_setup_usb_host(void)
{
	int err;

	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
	if (err)
		return err;

	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));

	return 0;
}

static int cm_fx6_setup_usb_otg(void)
{
	int err;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
	if (err) {
		printf("USB OTG pwr gpio request failed: %d\n", err);
		return err;
	}

	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
						MUX_PAD_CTRL(WEAK_PULLDOWN));
	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
	/* disable ext. charger detect, or it'll affect signal quality at dp. */
	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
}

int board_usb_phy_mode(int port)
{
	return USB_INIT_HOST;
}

int board_ehci_hcd_init(int port)
{
	int ret;
	u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);

	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
	if (port != 1)
		return 0;

	/* Set PWR polarity to match power switch's enable polarity */
	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
	if (ret)
		return ret;

	udelay(10);
	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
	if (ret)
		return ret;

	mdelay(1);

	return 0;
}

int board_ehci_power(int port, int on)
{
	if (port == 0)
		return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);

	return 0;
}
#else
static int cm_fx6_setup_usb_otg(void) { return 0; }
static int cm_fx6_setup_usb_host(void) { return 0; }
#endif

#ifdef CONFIG_FEC_MXC
#define ENET_PAD_CTRL		(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
				 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

static int mx6_rgmii_rework(struct phy_device *phydev)
{
	unsigned short val;

	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
	 * which cause ethernet link down/up issue, so disable SmartEEE
	 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= ~(0x1 << 8);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);

	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	val &= 0xffe3;
	val |= 0x18;
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);

	/* introduce tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	val |= 0x0100;
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		return phydev->drv->config(phydev);

	return 0;
}

static iomux_v3_cfg_t const enet_pads[] = {
	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
						MUX_PAD_CTRL(ENET_PAD_CTRL)),
};

static int handle_mac_address(char *env_var, uint eeprom_bus)
{
	unsigned char enetaddr[6];
	int rc;

	rc = eth_getenv_enetaddr(env_var, enetaddr);
	if (rc)
		return 0;

	rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
	if (rc)
		return rc;

	if (!is_valid_ethaddr(enetaddr))
		return -1;

	return eth_setenv_enetaddr(env_var, enetaddr);
}

#define SB_FX6_I2C_EEPROM_BUS	0
#define NO_MAC_ADDR		"No MAC address found for %s\n"
int board_eth_init(bd_t *bis)
{
	int err;

	if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
		printf(NO_MAC_ADDR, "primary NIC");

	if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
		printf(NO_MAC_ADDR, "secondary NIC");

	SETUP_IOMUX_PADS(enet_pads);
	/* phy reset */
	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
	if (err)
		printf("Etnernet NRST gpio request failed: %d\n", err);
	gpio_direction_output(CM_FX6_ENET_NRST, 0);
	udelay(500);
	gpio_set_value(CM_FX6_ENET_NRST, 1);
	enable_enet_clk(1);
	return cpu_eth_init(bis);
}
#endif

#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const nand_pads[] = {
	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
};

static void cm_fx6_setup_gpmi_nand(void)
{
	SETUP_IOMUX_PADS(nand_pads);
	/* Enable clock roots */
	enable_usdhc_clk(1, 3);
	enable_usdhc_clk(1, 4);

	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
			  MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
			  MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
}
#else
static void cm_fx6_setup_gpmi_nand(void) {}
#endif

#ifdef CONFIG_FSL_ESDHC
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC1_BASE_ADDR},
	{USDHC2_BASE_ADDR},
	{USDHC3_BASE_ADDR},
};

static enum mxc_clock usdhc_clk[3] = {
	MXC_ESDHC_CLK,
	MXC_ESDHC2_CLK,
	MXC_ESDHC3_CLK,
};

int board_mmc_init(bd_t *bis)
{
	int i;

	cm_fx6_set_usdhc_iomux();
	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
		usdhc_cfg[i].max_bus_width = 4;
		fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		enable_usdhc_clk(1, i);
	}

	return 0;
}
#endif

#ifdef CONFIG_MXC_SPI
int cm_fx6_setup_ecspi(void)
{
	cm_fx6_set_ecspi_iomux();
	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
}
#else
int cm_fx6_setup_ecspi(void) { return 0; }
#endif

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
	uint8_t enetaddr[6];

	/* MAC addr */
	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
		fdt_find_and_setprop(blob,
				     "/soc/aips-bus@02100000/ethernet@02188000",
				     "local-mac-address", enetaddr, 6, 1);
	}

	if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
		fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
				     enetaddr, 6, 1);
	}

	return 0;
}
#endif

int board_init(void)
{
	int ret;

	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	cm_fx6_setup_gpmi_nand();

	ret = cm_fx6_setup_ecspi();
	if (ret)
		printf("Warning: ECSPI setup failed: %d\n", ret);

	ret = cm_fx6_setup_usb_otg();
	if (ret)
		printf("Warning: USB OTG setup failed: %d\n", ret);

	ret = cm_fx6_setup_usb_host();
	if (ret)
		printf("Warning: USB host setup failed: %d\n", ret);

	/*
	 * cm-fx6 may have iSSD not assembled and in this case it has
	 * bypasses for a (m)SATA socket on the baseboard. The socketed
	 * device is not controlled by those GPIOs. So just print a warning
	 * if the setup fails.
	 */
	ret = cm_fx6_setup_issd();
	if (ret)
		printf("Warning: iSSD setup failed: %d\n", ret);

	/* Warn on failure but do not abort boot */
	ret = cm_fx6_setup_i2c();
	if (ret)
		printf("Warning: I2C setup failed: %d\n", ret);

	cm_fx6_setup_display();

	return 0;
}

int checkboard(void)
{
	puts("Board: CM-FX6\n");
	return 0;
}

void dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;

	switch (gd->ram_size) {
	case 0x10000000: /* DDR_16BIT_256MB */
		gd->bd->bi_dram[0].size = 0x10000000;
		gd->bd->bi_dram[1].size = 0;
		break;
	case 0x20000000: /* DDR_32BIT_512MB */
		gd->bd->bi_dram[0].size = 0x20000000;
		gd->bd->bi_dram[1].size = 0;
		break;
	case 0x40000000:
		if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
			gd->bd->bi_dram[0].size = 0x20000000;
			gd->bd->bi_dram[1].size = 0x20000000;
		} else { /* DDR_64BIT_1GB */
			gd->bd->bi_dram[0].size = 0x40000000;
			gd->bd->bi_dram[1].size = 0;
		}
		break;
	case 0x80000000: /* DDR_64BIT_2GB */
		gd->bd->bi_dram[0].size = 0x40000000;
		gd->bd->bi_dram[1].size = 0x40000000;
		break;
	case 0xEFF00000: /* DDR_64BIT_4GB */
		gd->bd->bi_dram[0].size = 0x70000000;
		gd->bd->bi_dram[1].size = 0x7FF00000;
		break;
	}
}

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	switch (gd->ram_size) {
	case 0x10000000:
	case 0x20000000:
	case 0x40000000:
	case 0x80000000:
		break;
	case 0xF0000000:
		gd->ram_size -= 0x100000;
		break;
	default:
		printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
		return -1;
	}

	return 0;
}

u32 get_board_rev(void)
{
	return cl_eeprom_get_board_rev();
}

static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
	.reg = (struct mxc_uart *)UART4_BASE,
};

U_BOOT_DEVICE(cm_fx6_serial) = {
	.name	= "serial_mxc",
	.platdata = &cm_fx6_mxc_serial_plat,
};
Commit	Line	Data
e32028a7 NK	1	/*
	2	* Board functions for Compulab CM-FX6 board
	3	*
	4	* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
	5	*
	6	* Author: Nikita Kiryanov <nikita@compulab.co.il>
	7	*
	8	* SPDX-License-Identifier: GPL-2.0+
	9	*/
	10
	11	#include <common.h>
3f0e935f	12	#include <dm.h>
e32028a7	13	#include <fsl_esdhc.h>
02b1343e NK	14	#include <miiphy.h>
02b1343e NK	15	#include <netdev.h>
4377859a	16	#include <errno.h>
d6276ab1	17	#include <usb.h>
02b1343e	18	#include <fdt_support.h>
206f38f7	19	#include <sata.h>
f82eb2fa	20	#include <splash.h>
a6b0652b	21	#include <asm/arch/crm_regs.h>
e32028a7	22	#include <asm/arch/sys_proto.h>
0f3effb9	23	#include <asm/arch/iomux.h>
deb94d61	24	#include <asm/arch/mxc_hdmi.h>
f42b2f60	25	#include <asm/imx-common/mxc_i2c.h>
206f38f7	26	#include <asm/imx-common/sata.h>
deb94d61	27	#include <asm/imx-common/video.h>
a6b0652b	28	#include <asm/io.h>
02b1343e	29	#include <asm/gpio.h>
86256b79	30	#include <dm/platform_data/serial_mxc.h>
e32028a7	31	#include "common.h"
f66113c0	32	#include "../common/eeprom.h"
3a236a35	33	#include "../common/common.h"
e32028a7 NK	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
3a236a35 NK	37	#ifdef CONFIG_SPLASH_SCREEN
	38	static struct splash_location cm_fx6_splash_locations[] = {
	39	{
	40	.name = "sf",
	41	.storage = SPLASH_STORAGE_SF,
	42	.offset = 0x100000,
	43	},
	44	};
	45
	46	int splash_screen_prepare(void)
	47	{
f82eb2fa NK	48	return splash_source_load(cm_fx6_splash_locations,
f82eb2fa NK	49	ARRAY_SIZE(cm_fx6_splash_locations));
3a236a35 NK	50	}
	51	#endif
	52
deb94d61 NK	53	#ifdef CONFIG_IMX_HDMI
	54	static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
	55	{
b406f903 NK	56	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	57	imx_setup_hdmi();
	58	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
deb94d61 NK	59	imx_enable_hdmi_phy();
	60	}
	61
4377859a NK	62	static struct display_info_t preset_hdmi_1024X768 = {
	63	.bus = -1,
	64	.addr = 0,
	65	.pixfmt = IPU_PIX_FMT_RGB24,
	66	.enable = cm_fx6_enable_hdmi,
	67	.mode = {
	68	.name = "HDMI",
	69	.refresh = 60,
	70	.xres = 1024,
	71	.yres = 768,
	72	.pixclock = 40385,
	73	.left_margin = 220,
	74	.right_margin = 40,
	75	.upper_margin = 21,
	76	.lower_margin = 7,
	77	.hsync_len = 60,
	78	.vsync_len = 10,
	79	.sync = FB_SYNC_EXT,
	80	.vmode = FB_VMODE_NONINTERLACED,
	81	}
deb94d61	82	};
deb94d61 NK	83
	84	static void cm_fx6_setup_display(void)
	85	{
75dbbbfd	86	struct iomuxc const iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
deb94d61 NK	87
deb94d61 NK	88	enable_ipu_clock();
75dbbbfd	89	clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
deb94d61	90	}
4377859a NK	91
	92	int board_video_skip(void)
	93	{
	94	int ret;
	95	struct display_info_t *preset;
33299499 NK	96	char const *panel = getenv("displaytype");
	97
	98	if (!panel) /* Also accept panel for backward compatibility */
	99	panel = getenv("panel");
4377859a NK	100
	101	if (!panel)
	102	return -ENOENT;
	103
	104	if (!strcmp(panel, "HDMI"))
	105	preset = &preset_hdmi_1024X768;
	106	else
	107	return -EINVAL;
	108
	109	ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
	110	if (ret) {
	111	printf("Can't init display %s: %d\n", preset->mode.name, ret);
	112	return ret;
	113	}
	114
	115	preset->enable(preset);
	116	printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
	117	preset->mode.yres);
	118
	119	return 0;
	120	}
deb94d61 NK	121	#else
	122	static inline void cm_fx6_setup_display(void) {}
	123	#endif /* CONFIG_VIDEO_IPUV3 */
	124
206f38f7 NK	125	#ifdef CONFIG_DWC_AHSATA
	126	static int cm_fx6_issd_gpios[] = {
	127	/* The order of the GPIOs in the array is important! */
b65cbab1	128	CM_FX6_SATA_LDO_EN,
206f38f7 NK	129	CM_FX6_SATA_PHY_SLP,
	130	CM_FX6_SATA_NRSTDLY,
	131	CM_FX6_SATA_PWREN,
	132	CM_FX6_SATA_NSTANDBY1,
	133	CM_FX6_SATA_NSTANDBY2,
206f38f7 NK	134	};
	135
	136	static void cm_fx6_sata_power(int on)
	137	{
	138	int i;
	139
	140	if (!on) { /* tell the iSSD that the power will be removed */
	141	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
	142	mdelay(10);
	143	}
	144
	145	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
	146	gpio_direction_output(cm_fx6_issd_gpios[i], on);
	147	udelay(100);
	148	}
	149
	150	if (!on) /* for compatibility lower the power loss interrupt */
	151	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	152	}
	153
	154	static iomux_v3_cfg_t const sata_pads[] = {
	155	/* SATA PWR */
	156	IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	157	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	158	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	159	IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	160	/* SATA CTRL */
	161	IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	162	IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	163	IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	164	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	165	IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	166	};
	167
8f488c1b	168	static int cm_fx6_setup_issd(void)
206f38f7	169	{
8f488c1b NK	170	int ret, i;
8f488c1b NK	171
206f38f7	172	SETUP_IOMUX_PADS(sata_pads);
206f38f7	173
8f488c1b NK	174	for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
	175	ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
	176	if (ret)
	177	return ret;
	178	}
	179
	180	ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
	181	if (ret)
	182	return ret;
	183
	184	return 0;
206f38f7 NK	185	}
	186
	187	#define CM_FX6_SATA_INIT_RETRIES 10
	188	int sata_initialize(void)
	189	{
	190	int err, i;
	191
8f488c1b NK	192	/* Make sure this gpio has logical 0 value */
	193	gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
	194	udelay(100);
8f488c1b NK	195	cm_fx6_sata_power(1);
8f488c1b NK	196
206f38f7 NK	197	for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
	198	err = setup_sata();
	199	if (err) {
	200	printf("SATA setup failed: %d\n", err);
	201	return err;
	202	}
	203
	204	udelay(100);
	205
	206	err = __sata_initialize();
	207	if (!err)
	208	break;
	209
	210	/* There is no device on the SATA port */
	211	if (sata_port_status(0, 0) == 0)
	212	break;
	213
	214	/* There's a device, but link not established. Retry */
	215	}
	216
	217	return err;
	218	}
9cad3544 NK	219
	220	int sata_stop(void)
	221	{
	222	__sata_stop();
	223	cm_fx6_sata_power(0);
	224	mdelay(250);
	225
	226	return 0;
	227	}
8f488c1b NK	228	#else
8f488c1b NK	229	static int cm_fx6_setup_issd(void) { return 0; }
206f38f7 NK	230	#endif
206f38f7 NK	231
f42b2f60 NK	232	#ifdef CONFIG_SYS_I2C_MXC
	233	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	234	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	235	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	236
	237	I2C_PADS(i2c0_pads,
	238	PAD_EIM_D21__I2C1_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	239	PAD_EIM_D21__GPIO3_IO21 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	240	IMX_GPIO_NR(3, 21),
	241	PAD_EIM_D28__I2C1_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	242	PAD_EIM_D28__GPIO3_IO28 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	243	IMX_GPIO_NR(3, 28));
	244
	245	I2C_PADS(i2c1_pads,
	246	PAD_KEY_COL3__I2C2_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	247	PAD_KEY_COL3__GPIO4_IO12 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	248	IMX_GPIO_NR(4, 12),
	249	PAD_KEY_ROW3__I2C2_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	250	PAD_KEY_ROW3__GPIO4_IO13 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	251	IMX_GPIO_NR(4, 13));
	252
	253	I2C_PADS(i2c2_pads,
	254	PAD_GPIO_3__I2C3_SCL \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	255	PAD_GPIO_3__GPIO1_IO03 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	256	IMX_GPIO_NR(1, 3),
	257	PAD_GPIO_6__I2C3_SDA \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	258	PAD_GPIO_6__GPIO1_IO06 \| MUX_PAD_CTRL(I2C_PAD_CTRL),
	259	IMX_GPIO_NR(1, 6));
	260
	261
edbf8b4f	262	static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
f42b2f60	263	{
edbf8b4f SG	264	int ret;
	265
	266	ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
	267	if (ret)
	268	printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
	269
	270	return ret;
	271	}
	272
	273	static int cm_fx6_setup_i2c(void)
	274	{
	275	int ret = 0, err;
	276
	277	/* i2c<x>_pads are wierd macro variables; we can't use an array */
	278	err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
	279	if (err)
	280	ret = err;
	281	err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
	282	if (err)
	283	ret = err;
	284	err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
	285	if (err)
	286	ret = err;
	287
	288	return ret;
f42b2f60 NK	289	}
f42b2f60 NK	290	#else
edbf8b4f	291	static int cm_fx6_setup_i2c(void) { return 0; }
f42b2f60 NK	292	#endif
f42b2f60 NK	293
0f3effb9 NK	294	#ifdef CONFIG_USB_EHCI_MX6
	295	#define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN \| \
	296	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	297	PAD_CTL_HYS \| PAD_CTL_SRE_SLOW)
8f488c1b NK	298	#define MX6_USBNC_BASEADDR 0x2184800
8f488c1b NK	299	#define USBNC_USB_H1_PWR_POL (1 << 9)
0f3effb9	300
8f488c1b	301	static int cm_fx6_setup_usb_host(void)
0f3effb9 NK	302	{
	303	int err;
	304
	305	err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
8f488c1b NK	306	if (err)
8f488c1b NK	307	return err;
0f3effb9	308
8f488c1b	309	SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR \| MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9	310	SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 \| MUX_PAD_CTRL(NO_PAD_CTRL));
0f3effb9 NK	311
	312	return 0;
	313	}
	314
8f488c1b	315	static int cm_fx6_setup_usb_otg(void)
0f3effb9	316	{
8f488c1b	317	int err;
0f3effb9 NK	318	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
0f3effb9 NK	319
8f488c1b NK	320	err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
	321	if (err) {
	322	printf("USB OTG pwr gpio request failed: %d\n", err);
	323	return err;
0f3effb9 NK	324	}
	325
	326	SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(NO_PAD_CTRL));
	327	SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID \|
	328	MUX_PAD_CTRL(WEAK_PULLDOWN));
	329	clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
	330	/* disable ext. charger detect, or it'll affect signal quality at dp. */
	331	return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
	332	}
	333
d6276ab1 NK	334	int board_usb_phy_mode(int port)
	335	{
	336	return USB_INIT_HOST;
	337	}
	338
0f3effb9 NK	339	int board_ehci_hcd_init(int port)
0f3effb9 NK	340	{
8f488c1b	341	int ret;
0f3effb9 NK	342	u32 usbnc_usb_uh1_ctrl = (u32 )(MX6_USBNC_BASEADDR + 4);
0f3effb9 NK	343
8f488c1b NK	344	/* Only 1 host controller in use. port 0 is OTG & needs no attention */
	345	if (port != 1)
	346	return 0;
	347
	348	/* Set PWR polarity to match power switch's enable polarity */
	349	setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
	350	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
	351	if (ret)
	352	return ret;
	353
	354	udelay(10);
	355	ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
	356	if (ret)
	357	return ret;
	358
	359	mdelay(1);
0f3effb9 NK	360
	361	return 0;
	362	}
	363
	364	int board_ehci_power(int port, int on)
	365	{
	366	if (port == 0)
	367	return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
	368
	369	return 0;
	370	}
8f488c1b NK	371	#else
	372	static int cm_fx6_setup_usb_otg(void) { return 0; }
	373	static int cm_fx6_setup_usb_host(void) { return 0; }
0f3effb9 NK	374	#endif
0f3effb9 NK	375
02b1343e NK	376	#ifdef CONFIG_FEC_MXC
	377	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
	378	PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
	379
	380	static int mx6_rgmii_rework(struct phy_device *phydev)
	381	{
	382	unsigned short val;
	383
	384	/* Ar8031 phy SmartEEE feature cause link status generates glitch,
	385	* which cause ethernet link down/up issue, so disable SmartEEE
	386	*/
	387	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
	388	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
	389	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
	390	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	391	val &= ~(0x1 << 8);
	392	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	393
	394	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
	395	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	396	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	397	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	398
	399	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
	400	val &= 0xffe3;
	401	val \|= 0x18;
	402	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
	403
	404	/* introduce tx clock delay */
	405	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
	406	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
	407	val \|= 0x0100;
	408	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
	409
	410	return 0;
	411	}
	412
	413	int board_phy_config(struct phy_device *phydev)
	414	{
	415	mx6_rgmii_rework(phydev);
	416
	417	if (phydev->drv->config)
	418	return phydev->drv->config(phydev);
	419
	420	return 0;
	421	}
	422
	423	static iomux_v3_cfg_t const enet_pads[] = {
	424	IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	425	IOMUX_PADS(PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	426	IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	427	IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	428	IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	429	IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	430	IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	431	IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	432	IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	433	IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	434	IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	435	IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL)),
	436	IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	437	IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	438	IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 \| MUX_PAD_CTRL(0x84)),
	439	IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK \|
440	MUX_PAD_CTRL(ENET_PAD_CTRL)),
441	IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL \|
442	MUX_PAD_CTRL(ENET_PAD_CTRL)),
443	IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL \|
444	MUX_PAD_CTRL(ENET_PAD_CTRL)),
445	};
446
eab29802	447	static int handle_mac_address(char *env_var, uint eeprom_bus)
f66113c0 NK	448	{
	449	unsigned char enetaddr[6];
	450	int rc;
	451
eab29802	452	rc = eth_getenv_enetaddr(env_var, enetaddr);
f66113c0 NK	453	if (rc)
	454	return 0;
	455
eab29802	456	rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
f66113c0 NK	457	if (rc)
	458	return rc;
	459
0adb5b76	460	if (!is_valid_ethaddr(enetaddr))
f66113c0 NK	461	return -1;
f66113c0 NK	462
eab29802	463	return eth_setenv_enetaddr(env_var, enetaddr);
f66113c0 NK	464	}
f66113c0 NK	465
eab29802 NK	466	#define SB_FX6_I2C_EEPROM_BUS 0
eab29802 NK	467	#define NO_MAC_ADDR "No MAC address found for %s\n"
02b1343e NK	468	int board_eth_init(bd_t *bis)
02b1343e NK	469	{
8f488c1b NK	470	int err;
8f488c1b NK	471
eab29802 NK	472	if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
	473	printf(NO_MAC_ADDR, "primary NIC");
	474
	475	if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
	476	printf(NO_MAC_ADDR, "secondary NIC");
f66113c0	477
02b1343e NK	478	SETUP_IOMUX_PADS(enet_pads);
02b1343e NK	479	/* phy reset */
8f488c1b NK	480	err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
	481	if (err)
	482	printf("Etnernet NRST gpio request failed: %d\n", err);
02b1343e NK	483	gpio_direction_output(CM_FX6_ENET_NRST, 0);
	484	udelay(500);
	485	gpio_set_value(CM_FX6_ENET_NRST, 1);
	486	enable_enet_clk(1);
	487	return cpu_eth_init(bis);
	488	}
	489	#endif
	490
a6b0652b NK	491	#ifdef CONFIG_NAND_MXS
	492	static iomux_v3_cfg_t const nand_pads[] = {
	493	IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	494	IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	495	IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	496	IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	497	IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	498	IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	499	IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	500	IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	501	IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	502	IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	503	IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	504	IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	505	IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	506	IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	507	};
	508
	509	static void cm_fx6_setup_gpmi_nand(void)
	510	{
	511	SETUP_IOMUX_PADS(nand_pads);
	512	/* Enable clock roots */
	513	enable_usdhc_clk(1, 3);
	514	enable_usdhc_clk(1, 4);
	515
	516	setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) \|
	517	MXC_CCM_CS2CDR_ENFC_CLK_PRED(1) \|
	518	MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
	519	}
	520	#else
	521	static void cm_fx6_setup_gpmi_nand(void) {}
	522	#endif
	523
e32028a7 NK	524	#ifdef CONFIG_FSL_ESDHC
	525	static struct fsl_esdhc_cfg usdhc_cfg[3] = {
	526	{USDHC1_BASE_ADDR},
	527	{USDHC2_BASE_ADDR},
	528	{USDHC3_BASE_ADDR},
	529	};
	530
	531	static enum mxc_clock usdhc_clk[3] = {
	532	MXC_ESDHC_CLK,
	533	MXC_ESDHC2_CLK,
	534	MXC_ESDHC3_CLK,
	535	};
	536
	537	int board_mmc_init(bd_t *bis)
	538	{
	539	int i;
	540
	541	cm_fx6_set_usdhc_iomux();
	542	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	543	usdhc_cfg[i].sdhc_clk = mxc_get_clock(usdhc_clk[i]);
	544	usdhc_cfg[i].max_bus_width = 4;
	545	fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
	546	enable_usdhc_clk(1, i);
	547	}
	548
	549	return 0;
	550	}
	551	#endif
	552
8f488c1b NK	553	#ifdef CONFIG_MXC_SPI
	554	int cm_fx6_setup_ecspi(void)
	555	{
	556	cm_fx6_set_ecspi_iomux();
	557	return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
	558	}
	559	#else
	560	int cm_fx6_setup_ecspi(void) { return 0; }
	561	#endif
	562
02b1343e	563	#ifdef CONFIG_OF_BOARD_SETUP
e895a4b0	564	int ft_board_setup(void blob, bd_t bd)
02b1343e NK	565	{
	566	uint8_t enetaddr[6];
	567
	568	/* MAC addr */
	569	if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
cc67f4a6 NK	570	fdt_find_and_setprop(blob,
	571	"/soc/aips-bus@02100000/ethernet@02188000",
	572	"local-mac-address", enetaddr, 6, 1);
02b1343e	573	}
e895a4b0	574
eab29802 NK	575	if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
	576	fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
	577	enetaddr, 6, 1);
	578	}
	579
e895a4b0	580	return 0;
02b1343e NK	581	}
	582	#endif
	583
e32028a7 NK	584	int board_init(void)
e32028a7 NK	585	{
edbf8b4f SG	586	int ret;
edbf8b4f SG	587
e32028a7	588	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
a6b0652b	589	cm_fx6_setup_gpmi_nand();
edbf8b4f	590
8f488c1b NK	591	ret = cm_fx6_setup_ecspi();
	592	if (ret)
	593	printf("Warning: ECSPI setup failed: %d\n", ret);
	594
	595	ret = cm_fx6_setup_usb_otg();
	596	if (ret)
	597	printf("Warning: USB OTG setup failed: %d\n", ret);
	598
	599	ret = cm_fx6_setup_usb_host();
	600	if (ret)
	601	printf("Warning: USB host setup failed: %d\n", ret);
	602
	603	/*
	604	* cm-fx6 may have iSSD not assembled and in this case it has
	605	* bypasses for a (m)SATA socket on the baseboard. The socketed
	606	* device is not controlled by those GPIOs. So just print a warning
	607	* if the setup fails.
	608	*/
	609	ret = cm_fx6_setup_issd();
	610	if (ret)
	611	printf("Warning: iSSD setup failed: %d\n", ret);
	612
edbf8b4f SG	613	/* Warn on failure but do not abort boot */
	614	ret = cm_fx6_setup_i2c();
	615	if (ret)
	616	printf("Warning: I2C setup failed: %d\n", ret);
a6b0652b	617
deb94d61 NK	618	cm_fx6_setup_display();
deb94d61 NK	619
e32028a7 NK	620	return 0;
	621	}
	622
	623	int checkboard(void)
	624	{
	625	puts("Board: CM-FX6\n");
	626	return 0;
	627	}
	628
	629	void dram_init_banksize(void)
	630	{
	631	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	632	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	633
	634	switch (gd->ram_size) {
	635	case 0x10000000: /* DDR_16BIT_256MB */
	636	gd->bd->bi_dram[0].size = 0x10000000;
	637	gd->bd->bi_dram[1].size = 0;
	638	break;
	639	case 0x20000000: /* DDR_32BIT_512MB */
	640	gd->bd->bi_dram[0].size = 0x20000000;
	641	gd->bd->bi_dram[1].size = 0;
	642	break;
	643	case 0x40000000:
	644	if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
	645	gd->bd->bi_dram[0].size = 0x20000000;
	646	gd->bd->bi_dram[1].size = 0x20000000;
	647	} else { /* DDR_64BIT_1GB */
	648	gd->bd->bi_dram[0].size = 0x40000000;
	649	gd->bd->bi_dram[1].size = 0;
	650	}
	651	break;
	652	case 0x80000000: /* DDR_64BIT_2GB */
	653	gd->bd->bi_dram[0].size = 0x40000000;
	654	gd->bd->bi_dram[1].size = 0x40000000;
	655	break;
	656	case 0xEFF00000: /* DDR_64BIT_4GB */
	657	gd->bd->bi_dram[0].size = 0x70000000;
	658	gd->bd->bi_dram[1].size = 0x7FF00000;
	659	break;
	660	}
	661	}
	662
	663	int dram_init(void)
	664	{
	665	gd->ram_size = imx_ddr_size();
	666	switch (gd->ram_size) {
	667	case 0x10000000:
	668	case 0x20000000:
	669	case 0x40000000:
	670	case 0x80000000:
	671	break;
	672	case 0xF0000000:
	673	gd->ram_size -= 0x100000;
	674	break;
	675	default:
	676	printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
	677	return -1;
	678	}
	679
	680	return 0;
	681	}
f66113c0 NK	682
	683	u32 get_board_rev(void)
	684	{
	685	return cl_eeprom_get_board_rev();
	686	}
	687
3f0e935f SG	688	static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
	689	.reg = (struct mxc_uart *)UART4_BASE,
	690	};
	691
	692	U_BOOT_DEVICE(cm_fx6_serial) = {
	693	.name = "serial_mxc",
	694	.platdata = &cm_fx6_mxc_serial_plat,
	695	};